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    Memory support provided with elements of ferroelectric material and non-destructive reading method thereof
    96.
    发明公开
    Memory support provided with elements of ferroelectric material and non-destructive reading method thereof 审中-公开
    物理化学物质和化学物质和化学物质Leseverfahrendafür

    公开(公告)号：EP2482286A1

    公开(公告)日：2012-08-01

    申请号：EP12153545.4

    申请日：2012-02-01

    Applicant: STMicroelectronics Srl

    Inventor： Scalia, Antonio Maria ,  Greco, Maurizio

    IPC: G11C11/22

    CPC classification number: G11C11/22 ,  B23Q1/0018 ,  B23Q3/061 ,  B23Q3/062 ,  B23Q3/082

    Abstract: A method for non-destructive reading of a logic datum to be read stored in a memory (10) including a first word line (18a), a first bit line (16a), a second bit line (17a), and a first ferroelectric transistor (14) including a layer of ferroelectric material (26) in a stable state of polarization that can be associated to a high logic value or a low logic value of the logic datum to be read; the ferroelectric transistor is connected between the first and second bit lines, and has a control terminal (20c) coupled to the first word line. The method comprises the steps of: applying to the first word line (18a) a reading voltage (V read ) such as not to cause a variation of the stable state of polarization of the layer of ferroelectric material (26); generating a difference of potential (V sense ) between the first and second bit lines (16a, 17a); generating an output current (i TOT ); comparing the output current (i TOT ) with a plurality of comparison values; and determining the logic value of the logic datum to be read on the basis of the comparison.

    Abstract translation: 一种用于对包含第一字线（18a），第一位线（16a），第二位线（17a）和第一铁电体（17a）的存储器（10）中存储的要读取的逻辑数据进行非破坏性读取的方法 晶体管（14）包括处于稳定的极化状态的铁电材料层（26），其可以与待读取的逻辑数据的高逻辑值或低逻辑值相关联; 铁电晶体管连接在第一和第二位线之间，并且具有耦合到第一字线的控制端子（20c）。 该方法包括以下步骤：向第一字线（18a）施加读取电压（V读），例如不引起铁电材料层26的稳定极化状态的变化; 产生第一和第二位线（16a，17a）之间的电位差（V sense）; 产生输出电流（i TOT）; 将输出电流（i TOT）与多个比较值进行比较; 并基于该比较来确定要读取的逻辑数据的逻辑值。

    Interface system, and corresponding integrated circuit and method
    97.
    发明公开
    Interface system, and corresponding integrated circuit and method 有权
    Schnittstellensystem，entsprechende integrierte Schaltung und Verfahren

    公开(公告)号：EP2466479A1

    公开(公告)日：2012-06-20

    申请号：EP11193208.3

    申请日：2011-12-13

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Srl

    Inventor： Mangano, Daniele ,  Pisasale, Salvatore ,  Urzi', Ignazio Antonino

    IPC: G06F13/40

    CPC classification number: G06F13/4059 ,  G06F1/12 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/42

    Abstract: An interface system (10) for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal (CLK RX), a first data signal (DATA) when a first control signal (REQ) indicates that the first data signal (DATA) contains valid data, and wherein the asynchronous circuit (4) generates a second data signal (ADATA) according to an asynchronous communication protocol.
    In particular, the system comprises:
    - a First-In First-Out memory (18) comprising a plurality of memory locations,
    - a control circuit (20) configured for:
    a) asynchronously writing (204, 206) the second data signal (ADATA) in the memory (18) when the second data signal (ADATA) indicates the start of a communication, and
    b) synchronously reading (200, 202) the second data signal (ADATA') from the memory (18) in response to a clock signal (CLK_RX),

    - a conversion circuit (12) configured for decoding, according to a asynchronous communication protocol, the second data signal (ADATA') read from the memory (18) in a decoded data signal, wherein the decoded data signal corresponds to the first data signal (DATA).

    Abstract translation: 一种用于将异步电路与同步电路接口的接口系统（10），其中当第一控制信号（REQ）指示第一数据信号（REQ））时，同步电路响应于时钟信号（CLK RX）采样第一数据信号 第一数据信号（DATA）包含有效数据，并且其中异步电路（4）根据异步通信协议生成第二数据信号（ADATA）。 特别地，该系统包括： - 包括多个存储器位置的先​​进先出存储器（18）， - 控制电路（20），被配置为：a）异步地将第二数据信号（204,206）写入（204,206） ADATA）在第二数据信号（ADATA）指示通信的开始时存储在存储器（18）中，以及b）响应于存储器（18）同步地从存储器（18）读取（200,202）第二数据信号（ADATA'） 时钟信号（CLK_RX）， - 转换电路（12），被配置为根据异步通信协议在解码数据信号中解码从存储器（18）读取的第二数据信号（ADATA'），其中解码数据 信号对应于第一数据信号（DATA）。

    Communication system, and corresponding integrated circuit and method
    98.
    发明公开
    Communication system, and corresponding integrated circuit and method 有权
    Kommunikationssystem，und entsprechende integrierte Schaltung und Verfahren

    公开(公告)号：EP2466478A1

    公开(公告)日：2012-06-20

    申请号：EP11193192.9

    申请日：2011-12-13

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Srl

    Inventor： Mangano, Daniele ,  Urzi', Ignazio Antonino

    IPC: G06F13/40

    CPC classification number: G06F13/4059

    Abstract: A communication system for interfacing a first synchronous circuit (1) with a second synchronous circuit (6). The system comprising a first interface system (3) and a second interface system (5).
    The first interface system (3) receives data (TX_DATA) from the first synchronous circuit (1), and encodes (32) the data (TX_DATA) according to an asynchronous communication protocol. The encoded data (ADATA) are transmitted over a communication channel to the second interface system (5).
    The second interface system (5) decodes the data (ADATA) and transmits the decoded data (RX_DATA) to the second synchronous circuit (6).
    In particular, the first interface system (3) comprises a first First-In First-Out memory for storing temporarily the data (TX_DATA) received from the first synchronous circuit (1) and the second interface system (5) comprises a second First-In First-Out memory for storing temporarily the data (ADATA) transmitted over the communication channel, and the communication system is configured for transmitting to the first synchronous circuit (1) a control signal (TX_ACK') determined (310) as a function of the state of the first and the second memory.

    Abstract translation: 一种用于将第一同步电路（1）与第二同步电路（6）接口的通信系统。 该系统包括第一接口系统（3）和第二接口系统（5）。 第一接口系统（3）从第一同步电路（1）接收数据（TX_DATA），并根据异步通信协议对数据（TX_DATA）进行编码（32）。 编码数据（ADATA）通过通信信道发送到第二接口系统（5）。 第二接口系统（5）解码数据（ADATA）并将解码数据（RX_DATA）发送到第二同步电路（6）。 特别地，第一接口系统（3）包括用于临时存储从第一同步电路（1）接收的数据（TX_DATA）的第一先入先出存储器，并且第二接口系统（5）包括第二第一接收系统 在先出存储器中，用于临时存储通过通信信道发送的数据（ADATA），并且通信系统被配置为向第一同步电路（1）发送确定为（310）的函数的控制信号（TX_ACK'）， 第一和第二个记忆的状态。

    Interface system, and corresponding integrated circuit and method
    99.
    发明公开
    Interface system, and corresponding integrated circuit and method 有权
    接口系统以及相应的集成电路和方法

    公开(公告)号：EP2466477A1

    公开(公告)日：2012-06-20

    申请号：EP11192731.5

    申请日：2011-12-09

    Applicant: STMicroelectronics Srl

    Inventor： Mangano, Daniele ,  Pisasale, Salvatore

    IPC: G06F13/40

    CPC classification number: G06F13/4059

    Abstract: An interface system (10) for interfacing a synchronous circuit with an asynchronous circuit, wherein the synchronous circuit generates, in response to a clock signal (CLK TX), a first control signal (REQ) indicating the fact that a first data signal (DATA) contains valid data, and wherein the asynchronous circuit (4) generates, according to an asynchronous communication protocol, a second control signal (AACK) indicating the state of transmission of a second data signal (ADATA).
    In particular, the system comprises:
    - a conversion circuit (12), configured for converting, according to the asynchronous communication protocol, the first data signal (DATA) into an encoded data signal (ADATA'),
    - a First-in First-out memory (18) comprising a plurality of memory locations, wherein the signal currently read from the memory (18) corresponds to the second data signal (ADATA), and
    - a control circuit configured for:
    a) writing the encoded data signal (ADATA') in the memory (18) in a synchronous way in response to the clock signal (CLK TX), and
    b) reading the second data signal (ADATA) from the memory (18) in an asynchronous way in response to the second control signal (AACK).

    Abstract translation: 一种用于接口同步电路与异步电路的接口系统（10），其中同步电路响应于时钟信号（CLK TX）产生第一控制信号（REQ），该第一控制信号（REQ）指示第一数据信号（DATA ）包含有效数据，并且其中异步电路（4）根据异步通信协议生成指示第二数据信号（ADATA）的传输状态的第二控制信号（AACK）。 特别地，该系统包括： - 转换电路（12），被配置用于根据异步通信协议将第一数据信号（DATA）转换成编码数据信号（ADATA'）， - 先进先出 （18）包括多个存储位置，其中当前从存储器（18）读取的信号对应于第二数据信号（ADATA）;以及控制电路，被配置用于：a）将编码数据信号 '）响应于时钟信号（CLK TX）以同步方式存储在存储器（18）中，并且b）响应于第二控制以异步方式从存储器（18）读取第二数据信号（ADATA） 信号（AACK）。

    ELECTRONIC DEVICE WITH PROTECTION CIRCUIT
    100.
    发明公开
    ELECTRONIC DEVICE WITH PROTECTION CIRCUIT 有权
    带保护电路的电子器件

    公开(公告)号：EP2462671A1

    公开(公告)日：2012-06-13

    申请号：EP09848008.0

    申请日：2009-08-06

    Applicant: Freescale Semiconductor, Inc. ,  STMicroelectronics Srl

    Inventor： BODE, Hubert ,  GIACOMINI, Mauro

    IPC: H02H7/20

    CPC classification number: H01L27/0285 ,  H03K19/00315

    Abstract: An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.

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