公开(公告)号：KR100519750B1

公开(公告)日：2005-10-07

申请号：KR1020010025571

申请日：2001-05-10

Applicant: 삼성전자주식회사

Inventor： 송훈 ,  송기무 ,  김정우 ,  이은성 ,  우상현 ,  강석진 ,  황준식

IPC: H01L23/522

Abstract: 본 발명은 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체 및 그 제조방법에 관하여 개시한다. 저온소결 세라믹으로 실링된 칩 스케일 패키지 구조체는, MEMS 소자 또는 전자회로가 집적되어 있는 반도체칩; 상기 반도체칩의 상방에서 위치하는 저온소결 세라믹 소재; 및 상기 세라믹 소재와 상기 반도체칩 사이에 개재하여 그들간의 전기적 신호를 접속시키며 그중 외부에 형성된 것은 그들을 외부로부터 밀봉실링하는 실링부를 형성하는 솔더범프들;을 구비한다. 이에 따르면, 웨이퍼 레벨에서 칩스케일의 패키징이 가능해지고 밀봉실링이 되므로 습기의 영향을 방지할 수 있으며 낮은 온도에서의 본딩으로 열적 충격에 약한 제품에도 적용이 가능하며, 칩온칩(Chip On Chip) 기술에 의해 소형의 모듈의 구성이 가능해지는 효과가 있다.

公开(公告)号：KR1020040108309A

公开(公告)日：2004-12-23

申请号：KR1020030063362

申请日：2003-09-09

Applicant: 삼성전자주식회사

Inventor： 전상훈 ,  채수두 ,  김주형 ,  김정우

IPC: H01L27/115

Abstract: PURPOSE: An SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) memory device and a manufacturing method thereof are provided to keep a memory node layer in an amorphous state even under a high temperature MOS(Metal Oxide Semiconductor) process by using a high dielectric MON or MSiON layer as the memory node layer. CONSTITUTION: An SONOS memory device includes a semiconductor substrate(40) and a multi-functional device with a switching function and a data storing function. The multi-functional device includes a first and second impurity region(42,44) in the substrate, a channel region(46) between the first and second impurity regions, and a data storing laminate(60) formed on the substrate to align the first and second impurity regions. The data storing laminate is formed by depositing sequentially a tunneling oxide layer(48a), a memory node layer(50a), a blocking layer(52a) and an electrode layer(54a). The memory node layer is made of an MON layer or an MSiON layer.

Abstract translation: 目的：提供一种SONOS（硅氧化物 - 氮化物 - 氧化物 - 硅）存储器件及其制造方法，即使在高温MOS（金属氧化物半导体）工艺下，通过使用高 介质MON或MSiON层作为存储器节点层。 构成：SONOS存储器件包括半导体衬底（40）和具有开关功能和数据存储功能的多功能器件。 多功能器件包括衬底中的第一和第二杂质区（42,44），在第一和第二杂质区之间的沟道区（46）和形成在衬底上的数据存储叠层（60） 第一和第二杂质区域。 数据存储层叠体通过依次沉积隧穿氧化物层（48a），存储节点层（50a），阻挡层（52a）和电极层（54a）而形成。 存储节点层由MON层或MSiON层构成。

公开(公告)号：KR1020040093606A

公开(公告)日：2004-11-06

申请号：KR1020030027543

申请日：2003-04-30

Applicant: 삼성전자주식회사

Inventor： 채수두 ,  김정우 ,  이정현 ,  김문경 ,  황현상

IPC: H01L21/8247

CPC classification number: H01L29/792 ,  H01L21/28194 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833

Abstract: PURPOSE: A non-volatile semiconductor memory device is provided to control effectively trap density according to doping concentration and to improve operation speed by forming an OHA(Oxide-Hafnium oxide Aluminium oxide) layer in a gate stack structure. CONSTITUTION: A semiconductor substrate(40) includes a source(S) and a drain(D) spaced apart from each other. A gate stack structure for contacting the source and drain is formed on the semiconductor substrate. The gate stack structure is composed of a tunneling layer(42), the first trap material layer(44), the first insulating layer(46) and a gate electrode(48). The first trap material layer and the first insulating layer have larger permittivity than a nitride layer. The first oxide layer is formed between the tunneling layer and the first trap material layer. The second oxide layer is formed between the first trap material layer and the first insulating layer. The first oxide layer is made of Al2O3. The first insulating layer is made of one selected from a group consisting of HfO2, ZrO2, Ta2O5, and TiO2.

Abstract translation: 目的：提供一种非易失性半导体存储器件，用于根据掺杂浓度有效地控制阱密度，并通过在栅极堆叠结构中形成OHA（氧化物 - 氧化铪氧化铝）层来提高操作速度。 构成：半导体衬底（40）包括彼此间隔开的源极（S）和漏极（D）。 用于接触源极和漏极的栅极堆叠结构形成在半导体衬底上。 栅极堆叠结构由隧道层（42），第一陷阱材料层（44），第一绝缘层（46）和栅电极（48）组成。 第一陷阱材料层和第一绝缘层具有比氮化物层更大的介电常数。 第一氧化物层形成在隧道层和第一捕集材料层之间。 第二氧化物层形成在第一捕集材料层和第一绝缘层之间。 第一氧化物层由Al2O3制成。 第一绝缘层由选自HfO 2，ZrO 2，Ta 2 O 5和TiO 2的一种制成。

公开(公告)号：KR1020040071851A

公开(公告)日：2004-08-16

申请号：KR1020030007758

申请日：2003-02-07

Applicant: 삼성전자주식회사

Inventor： 채수두 ,  김정우 ,  김주형

IPC: H01L29/775

CPC classification number: B82Y10/00 ,  H01L29/7888 ,  Y10S977/937 ,  Y10S977/938

Abstract: PURPOSE: A single electron transistor with memory function is provided to precisely form an interval between trap layers and maintain high repeatability by forming the trap layers by a CMOS(complementary metal oxide semiconductor) process. CONSTITUTION: The first substrate(50) and an insulation layer are sequentially stacked. The second substrate(54) is formed on the insulation layer, separated into a source region(54S), a channel region(54C) and a drain region(54D). A tunneling layer is formed on the second substrate. At least two trap layers are formed on the tunneling layer at such an interval(D) that at least one quantum dot(56) is formed in the channel region. A gate electrode(60) in contact with the tunneling layer and the trap layers between the at least two trap layers is formed.

Abstract translation: 目的：提供具有记忆功能的单电子晶体管，以通过CMOS（互补金属氧化物半导体）工艺形成陷阱层，精确地形成陷阱层之间的间隔并保持高重复性。 构成：依次层叠第一基板（50）和绝缘层。 第二基板（54）形成在绝缘层上，分离为源极区（54S），沟道区（54C）和漏极区（54D）。 隧道层形成在第二基板上。 至少两个陷阱层以这样的间隔（D）形成在隧道层上，使得在沟道区域中形成至少一个量子点（56）。 形成与隧道层接触的栅电极（60）和至少两个陷阱层之间的捕获层。

公开(公告)号：KR1020040043044A

公开(公告)日：2004-05-22

申请号：KR1020020071042

申请日：2002-11-15

Applicant: 삼성전자주식회사 ,  대한민국(서울대학교 총장)

Inventor： 김정우 ,  박병국 ,  이종덕 ,  이용규

IPC: H01L27/115

CPC classification number: H01L29/7926 ,  G11C11/5628 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7923

Abstract: PURPOSE: A non-volatile SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) memory having a vertical channel, a manufacturing method thereof, and a program method are provided to be capable of improving the degree of integration. CONSTITUTION: A non-volatile SONOS memory having a vertical channel is provided with a substrate(101), the first insulating layer(103) deposited on the substrate, and a semiconductor layer(105) patterned into a predetermined type structure on the first insulating layer. At this time, the semiconductor layer includes a source and drain electrode spaced apart from each other. The non-volatile SONOS memory further includes the second insulating layer(107) between the source and drain electrode on the semiconductor layer, a memory layer(109) selectively deposited on the resultant structure, and a gate electrode(111) deposited on the memory layer for controlling the electron mobility of the memory layer. The memory layer includes an electron mobility channel and an electron storing layer.

Abstract translation: 目的：提供具有垂直通道的非易失性SONOS（硅氧化物 - 氮化物 - 氧化物 - 硅）存储器，其制造方法和程序方法，以能够提高集成度。 构成：具有垂直通道的非挥发性SONOS存储器设置有衬底（101），沉积在衬底上的第一绝缘层（103）和在第一绝缘层上图案化为预定类型结构的半导体层（105） 层。 此时，半导体层包括彼此间隔开的源极和漏极。 非易失性SONOS存储器还包括在半导体层上的源极和漏极之间的第二绝缘层（107），选择性地沉积在所得结构上的存储层（109）和沉积在存储器上的栅电极（111） 用于控制存储层的电子迁移率的层。 存储层包括电子迁移率通道和电子存储层。

公开(公告)号：KR100419233B1

公开(公告)日：2004-02-21

申请号：KR1020020012985

申请日：2002-03-11

Applicant: 삼성전자주식회사

Inventor： 이은성 ,  김정우 ,  송인상 ,  김종석 ,  이문철

IPC: B81C1/00

CPC classification number: B81B3/0078 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C2201/0107 ,  B81C2201/014 ,  H01H59/0009

Abstract: A method for fabricating a MEMS device having a fixing part, driving part, electrode part, and contact parts on a substrate. A driving electrode is formed on the substrate, and then an insulation layer is formed thereon. The insulation layer is patterned, and the regions of the insulation layer in which the fixing part and the contact parts are formed are etched. A metal layer is formed on the substrate. The metal layer is planarized down to the insulation layer, and the driving electrode is formed. A sacrificial layer is formed on the substrate, and a groove-shaped space is formed in a region in which the fixing part is formed. A MEMS structure layer is formed on the sacrificial layer. Sidewalls are formed in the groove-shaped space, and the fixing part and driving part are formed, leaving the sacrificial layer underneath the fixing part.

Abstract translation: 一种用于制造MEMS器件的方法，所述MEMS器件在基板上具有固定部分，驱动部分，电极部分和接触部分。 在基板上形成驱动电极，然后在其上形成绝缘层。 对绝缘层进行图案化，并且蚀刻其中形成有固定部分和接触部分的绝缘层的区域。 在衬底上形成金属层。 金属层被平坦化到绝缘层，并形成驱动电极。 牺牲层形成在基板上，并且在形成固定部的区域中形成槽状空间。 MEMS结构层形成在牺牲层上。 在槽形空间中形成侧壁，形成固定部分和驱动部分，在固定部分的下面留下牺牲层。 ＆lt;图像＆GT;

公开(公告)号：KR100414213B1

公开(公告)日：2004-01-07

申请号：KR1020010044449

申请日：2001-07-24

Applicant: 삼성전자주식회사

Inventor： 송원상 ,  김정우 ,  이창섭 ,  김삼영 ,  위영진 ,  박기철

IPC: G01R31/02

CPC classification number: G01R31/2853

Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule. The unit part has vias formed through an interlayer dielectric layer at the both ends of a tooth parallel part, two tooth parallel parts connected with the vias, respectively, and a length parallel part electrically connecting two tooth parallel parts.

Abstract translation: 在本发明中，测试集成电路互连的漏电保护可靠性的装置。 该装置具有至少一个梳状图案，蜿蜒状图案和对图案施加偏压并且在通孔周围形成的互连处形成最大场区的装置，即在组成该齿的齿部的端部处 梳状图案。 在本发明的一个结构中，梳状图案形成在一个水平面上，并且蛇形状图案具有分别与齿部对应的多个单位部分和连接相邻的两个单位部分的连接部分。 根据设计规则，每个单元部分与梳状图案形成在同一水平面上并且与齿部分分开最小设计长度。 单元部分具有通过在齿平行部分的两端处的层间介电层形成的通孔，分别与通路连接的两个齿平行部分和电连接两个齿平行部分的长度平行部分。

公开(公告)号：KR1020030073432A

公开(公告)日：2003-09-19

申请号：KR1020020012985

申请日：2002-03-11

Applicant: 삼성전자주식회사

Inventor： 이은성 ,  김정우 ,  송인상 ,  김종석 ,  이문철

IPC: B81C1/00

CPC classification number: B81B3/0078 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C2201/0107 ,  B81C2201/014 ,  H01H59/0009

Abstract: PURPOSE: A MEMS device and a method for fabricating the same are provided to improve reliability of the MEMS device with achieving a stable driving characteristic of the MEMS device. CONSTITUTION: A driving electrode layer(320) is formed on a substrate(310) by patterning a driving electrode. A planar mold is formed on the substrate(310) having the driving electrode layer(320). The planar mold functions as an insulating layer(330). After patterning the insulating layer(330), the insulating layer(330) formed in a predetermined area, in which a fixing section and a contact section are formed, is etched. Then, a metal layer(340) is formed on the substrate(310) including the fixing section and contact section.

Abstract translation: 目的：提供一种MEMS器件及其制造方法，以通过实现MEMS器件的稳定的驱动特性来提高MEMS器件的可靠性。 构成：通过对驱动电极进行构图，在基板（310）上形成驱动电极层（320）。 在具有驱动电极层（320）的基板（310）上形成平面模具。 平面模具用作绝缘层（330）。 在图案化绝缘层（330）之后，形成在其中形成有固定部分和接触部分的预定区域中的绝缘层（330）被蚀刻。 然后，在包括固定部和接触部的基板（310）上形成金属层（340）。

公开(公告)号：KR100387241B1

公开(公告)日：2003-06-12

申请号：KR1020010028689

申请日：2001-05-24

Applicant: 삼성전자주식회사

Inventor： 김종석 ,  송기무 ,  김정우 ,  이문철 ,  권영우 ,  김용권 ,  천창율

IPC: H01H59/00

Abstract: PURPOSE: An RF MEMS(Micro Electro Mechanical System) switch is provided to reduce an insertion loss when an RF switch is turned on and improve a signal separation characteristic when the RF switch is turned off. CONSTITUTION: An input signal line(112) and two output signal lines(114) are formed on a dielectric substrate(100). An RF ground is formed on both sides of the input signal line(112) and the output signal lines(114). A gap(116) is formed between the input signal line(112) and the output signal lines(114). A contact plate(130) is formed to an upper direction of the gap(116). A driving electrode(140) is formed at both sides of the gap(116). A plurality of anchors(142) are formed on the driving electrode(140). A plurality of driving beams(144) are extended to an opposite direction of the anchors(142). An insulating portion(160) is inserted between the driving beams(144) and the contact plate(130). An insulating layer is formed on an RF ground(120) contacted with the driving beams(144). The RF grounds(120) are connected each other with a bridge(150). The bridge(150) is formed with a pillar(152) and a beam(154).

Abstract translation: 目的：提供RF MEMS（微机电系统）开关，以减少RF开关打开时的插入损耗，并改善RF开关关闭时的信号分离特性。 构成：在电介质基板（100）上形成输入信号线（112）和两条输出信号线（114）。 在输入信号线（112）和输出信号线（114）的两侧形成RF地。 在输入信号线（112）和输出信号线（114）之间形成间隙（116）。 接触板（130）形成在间隙（116）的上方。 驱动电极（140）形成在间隙（116）的两侧。 在驱动电极（140）上形成多个锚（142）。 多个驱动梁（144）延伸到锚（142）的相反方向。 在驱动梁（144）和接触板（130）之间插入绝缘部分（160）。 在与驱动梁（144）接触的RF接地（120）上形成绝缘层。 RF接地（120）通过桥（150）相互连接。 桥（150）形成有柱（152）和梁（154）。

公开(公告)号：KR1020030009816A

公开(公告)日：2003-02-05

申请号：KR1020010044450

申请日：2001-07-24

Applicant: 삼성전자주식회사

Inventor： 송원상 ,  김정우 ,  이창섭 ,  김삼영 ,  위영진 ,  박기철

IPC: G01R31/02

CPC classification number: H01L22/34 ,  G01R31/2853 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: An apparatus of testing insulation reliability of integrated circuit wiring is provided to estimate a trouble point of a semiconductor device when an electric field is concentrated at a peripheral wiring of a multi-layer via. CONSTITUTION: A plurality of branch patterns(120) are formed on the same layer as an axis pattern(110) and are diverged into a vertical direction to the axis pattern. A comb pattern(100) is formed vertically to the branch patterns and the axis pattern at each end of the branch patterns, and has a plurality of comb via holes(130) formed so as to penetrate an interlayer insulation film. Two branch parallel parts(310) are formed parallel with the branch patterns. An axis parallel part(320) is parallel with the axis pattern, and is used to connect ends of the two branch parallel parts. A plurality of serpentine unit parts(340) are vertical to the two branch parallel parts at ends of the two branch parallel parts, and has serpentine via holes(330) formed so as to penetrate the interlayer insulation film. A serpentine pattern(300) is parallel with the axis pattern, and is formed on another wiring layer spaced apart by the branch parallel part and the interlayer insulation film. The serpentine pattern has a connection part(350) for connecting two units and is connected to two via holes formed adjacent to the units. A voltage applying means applies a voltage to the comb pattern and the serpentine pattern.

Abstract translation: 目的：提供一种测试集成电路布线的绝缘可靠性的装置，以便在电场集中在多层通孔的外围布线时估计半导体器件的故障点。 构成：多个分支图案（120）形成在与轴图案（110）相同的层上，并且分散成与轴图案的垂直方向。 梳状图案（100）垂直于分支图案和分支图案的每一端处的轴图案形成，并且具有形成为穿透层间绝缘膜的多个梳状通孔（130）。 两个分支平行部分（310）与分支图形平行地形成。 轴平行部分（320）与轴图案平行，用于连接两个分支平行部分的端部。 多个蛇形单元部分（340）在两个分支平行部分的端部处垂直于两个分支平行部分，并且具有形成为穿透层间绝缘膜的蛇形通孔（330）。 蛇形图案（300）与轴图案平行，并且形成在由分支平行部分和层间绝缘膜间隔开的另一布线层上。 蛇形图案具有用于连接两个单元的连接部分（350），并且连接到与单元相邻形成的两个通孔。 电压施加装置向梳形图案和蛇形图案施加电压。