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公开(公告)号:AU2013375140B2
公开(公告)日:2017-03-23
申请号:AU2013375140
申请日:2013-12-06
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , GSCHWIND MICHAEL KARL
IPC: G06F17/16
Abstract: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.
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公开(公告)号:MX2016011905A
公开(公告)日:2016-12-02
申请号:MX2016011905
申请日:2015-03-11
Applicant: IBM
Inventor: SLEGEL TIMOTHY , SCHWARZ ERIC MARK , JACOBI CHRISTIAN , FADI YUSUF BUSABA , MICHAEL KARL GSCHWIND , VALENTINA SALAPURA , HAROLD WADE CAIN III
Abstract: Las modalidades se relacionan con la implementación de un protocolo de coherencia. Un aspecto incluye enviar una petición de datos a un procesador remoto y recibir por medio de un procesador una respuesta del procesador remoto. La respuesta tiene un estado de transición de una transacción remota en el procesador remoto. El procesador agrega el estado de transacción de la transacción remota en el procesador remoto en la tabla de seguimiento de interferencia de transacción local.
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公开(公告)号:SG11201606098YA
公开(公告)日:2016-08-30
申请号:SG11201606098Y
申请日:2015-03-11
Applicant: IBM
Inventor: SCHWARZ ERIC MARK , BUSABA FADI YUSUF , GSCHWIND MICHAEL KARL , SLEGEL TIMOTHY , SALAPURA VALENTINA , JACOBI CHRISTIAN , CAIN III HAROLD WADE
Abstract: Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.
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公开(公告)号:GB2525356B
公开(公告)日:2016-03-23
申请号:GB201514700
申请日:2014-01-07
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK
IPC: G06F9/30
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公开(公告)号:ZA201400730B
公开(公告)日:2015-10-28
申请号:ZA201400730
申请日:2014-01-30
Applicant: IBM
Inventor: COPELAND REID , GAINEY JR CHARLES , SCHWARZ ERIC MARK , MITRAN MARCEL , SLEGEL TIMOTHY , CARLOUGH STEVEN
Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
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公开(公告)号:MX2015009458A
公开(公告)日:2015-09-24
申请号:MX2015009458
申请日:2013-12-06
Applicant: IBM
Inventor: SLEGEL TIMOTHY , SCHWARZ ERIC MARK , BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL
IPC: G06F17/16
Abstract: Se facilita el manejo de la excepción del vector. Se ejecuta una instrucción vectorial que opera en uno o más elementos de un registro del vector. Cuando una excepción se encuentra durante la ejecución de la instrucción, se proporciona un código de excepción del vector, que indica una posición dentro del registro del vector que causó la excepción. El código de excepción del vector también incluye una razón para la excepción.
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公开(公告)号:AU2013375139A1
公开(公告)日:2015-07-16
申请号:AU2013375139
申请日:2013-12-04
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK
IPC: G06F9/30
Abstract: A Vector Checksum instruction. Elements from a second operand are added together one- by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.
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公开(公告)号:SG11201404862RA
公开(公告)日:2014-09-26
申请号:SG11201404862R
申请日:2013-03-07
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , GSCHWIND MICHAEL KARL
Abstract: Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.
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公开(公告)号:AU2012373736A1
公开(公告)日:2014-09-11
申请号:AU2012373736
申请日:2012-11-15
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , JACOBI CHRISTIAN
IPC: G11C11/00
Abstract: A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.
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100.
公开(公告)号:AU2012373734A1
公开(公告)日:2014-09-11
申请号:AU2012373734
申请日:2012-11-15
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , SLEGEL TIMOTHY , SCHWARZ ERIC MARK , JACOBI CHRISTIAN
IPC: G06F12/10
Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
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