Vector exception code
    91.
    发明专利

    公开(公告)号:AU2013375140B2

    公开(公告)日:2017-03-23

    申请号:AU2013375140

    申请日:2013-12-06

    Applicant: IBM

    Abstract: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.

    CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT

    公开(公告)号:ZA201400730B

    公开(公告)日:2015-10-28

    申请号:ZA201400730

    申请日:2014-01-30

    Applicant: IBM

    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

    CODIGO DE EXCEPCION DEL VECTOR.
    96.
    发明专利

    公开(公告)号:MX2015009458A

    公开(公告)日:2015-09-24

    申请号:MX2015009458

    申请日:2013-12-06

    Applicant: IBM

    Abstract: Se facilita el manejo de la excepción del vector. Se ejecuta una instrucción vectorial que opera en uno o más elementos de un registro del vector. Cuando una excepción se encuentra durante la ejecución de la instrucción, se proporciona un código de excepción del vector, que indica una posición dentro del registro del vector que causó la excepción. El código de excepción del vector también incluye una razón para la excepción.

    Vector Checksum instruction
    97.
    发明专利

    公开(公告)号:AU2013375139A1

    公开(公告)日:2015-07-16

    申请号:AU2013375139

    申请日:2013-12-04

    Applicant: IBM

    Abstract: A Vector Checksum instruction. Elements from a second operand are added together one- by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

    VECTOR FIND ELEMENT NOT EQUAL INSTRUCTION

    公开(公告)号:SG11201404862RA

    公开(公告)日:2014-09-26

    申请号:SG11201404862R

    申请日:2013-03-07

    Applicant: IBM

    Abstract: Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.

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