公开(公告)号：WO1998002954A1

公开(公告)日：1998-01-22

申请号：PCT/US1997009702

申请日：1997-06-23

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  McCUTCHAN, Dan, R. ,  SAMARAS, William, A. ,  AYERS, David, J.

IPC: H02M01/00

CPC classification number: H01R12/721 ,  H01R12/7088 ,  H05K1/141 ,  H05K1/18 ,  H05K3/301 ,  H05K7/1092

Abstract: A power delivery system includes a circuit board (11), a power consuming module (31) and a dc-dc converter (15). The printed circuit board (11) has on it a first signal connector (17), a pair of first contacts (21, 23) to which a first voltage is supplied, spaced from said connector (17), and fasteners (27) spaced from said pair of first contacts (21, 23). The power consuming module (31) has a second signal connector (19), mating with the first signal connector (17), and has respective upper and lower power pads (33 and 35) for receiving low voltage power. The dc-dc converter (15) converts the first voltage to a lower voltage. The dc-dc converter (15) has a pair of second contacts contacting said pair of first contacts (21, 23), surfaces (47) mating with said fasteners (27) and holding the converter (15) on the printed circuit board (11) such that said second contacts are in firm contact with said first contacts (21, 23), and a laterally extending connector (37) having upper and lower contacts supplying the lower voltage and engaging the upper and lower power pads (33 and 35) of the power consuming module (31).

Abstract translation: 电力输送系统包括电路板（11），功耗模块（31）和dc-dc转换器（15）。 印刷电路板（11）上具有第一信号连接器（17），与所述连接器（17）间隔开的与供给第一电压的一对第一触点（21,23）以及间隔开的紧固件（27） 从所述一对第一触点（21,23）开始。 功率消耗模块（31）具有与第一信号连接器（17）配合的第二信号连接器（19），并且具有用于接收低电压功率的相应的上和下电源焊盘（33和35）。 DC-DC转换器（15）将第一电压转换成较低的电压。 DC-DC转换器（15）具有接触所述一对第一触头（21,23）的一对第二触点，与所述紧固件（27）配合的表面（47）并将转换器（15）保持在印刷电路板 11），使得所述第二触点与所述第一触头（21,23）牢固接触，以及横向延伸的连接器（37），其具有提供较低电压的上部和下部触头，并且与上部和下部电源焊盘（33和35）接合 ）的功率消耗模块（31）。

公开(公告)号：WO1998000785A1

公开(公告)日：1998-01-08

申请号：PCT/US1997010655

申请日：1997-06-18

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CHO, Sung-Soo ,  CHI, Chao-Hsin ,  CHANG, David

IPC: G06F12/02

CPC classification number: G06F13/404 ,  G06F13/4027

Abstract: A computer system has a first bus (301), a first bus bridge (302), and a second bus bridge (304). The first bridge (302) connects the first bus (301) to a second bus (303) and the second bridge (304) connects the first bus (301) to a third bus (305). Normally, the first bridge (302) behaves as the only subtractive decode agent on the first bus (301), claiming all transactions initiated on the first bus (301) that target agents on the second bus (303) or the third bus (305). If the first bridge (302) claims a transaction targetting an agent on the third bus (305), the first bridge (302) transfers the responsibility to respond to the transaction to the second bridge (304).

Abstract translation: 计算机系统具有第一总线（301），第一总线桥（302）和第二总线桥（304）。 第一桥（302）将第一总线（301）连接到第二总线（303），第二桥（304）将第一总线（301）连接到第三总线（305）。 通常，第一桥（302）在第一总线（301）上表现为唯一的减法解码器，声称在第一总线（301）上发起的目标代理在第二总线（303）或第三总线（305）上发起的所有事务 ）。 如果第一桥接器（302）要求在第三总线（305）上针对代理的事务，则第一桥接器（302）将负责将该事务转移给第二桥接器（304）。

公开(公告)号：WO1998000778A1

公开(公告)日：1998-01-08

申请号：PCT/US1997011153

申请日：1997-06-26

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SHARANGPANI, Harshvardhan, P. ,  HAMMOND, Gary, N. ,  MULDER, Hans, J. ,  ARORA, Judge, K.

IPC: G06F09/00

CPC classification number: G06F9/3804 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3863

Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit (304) fetches instructions to be processed and branch prediction logic (336) coupled to the fetch unit (304) predicts the resolution of the condition. The branch prediction logic (336) of the invention also determines whether the resolution logic is likely to be predicted accurately. resolution of the condition is unlikely to be predicted accurately. Stream management logic (314) responsive to the branch prediction logic (336) directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if the resolution of the condition is unlikely to be predicted accurately. Results of properly executed instructions are then committed to architectural state in program order. In this manner, the invention reduces penalty related to mispredictions.

Abstract translation: 一种用于在程序流中有效处理指令的微处理器，包括诸如分支指令之类的条件程序流程控制指令。 条件程序流程控制指令如果条件被解析为满足，则针对要处理的第一代码部分，以及如果条件被解析为不满足则要处理的第二代码部分。 提取单元（304）取出待处理的指令，并且耦合到提取单元（304）的分支预测逻辑（336）预测条件的分辨率。 本发明的分支预测逻辑（336）还确定分辨率逻辑是否可能被准确预测。 条件的分辨率不可能准确预测。 响应于分支预测逻辑（336）的流管理逻辑（314）在解决条件之前指导来自第一和第二代码部分的指令的推测性处理，如果不可能准确地预测该条件的分辨率。 然后，正确执行的指令的结果将以程序顺序提交到架构状态。 以这种方式，本发明减少了与错误预测相关的惩罚。

公开(公告)号：WO1997048052A1

公开(公告)日：1997-12-18

申请号：PCT/US1997009059

申请日：1997-05-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SOLOMON, Gary ,  RABE, Jeff ,  ABRAMSON, Darren

IPC: G06F13/00

CPC classification number: G06F13/4018 ,  G06F13/4036

Abstract: A collection buffering scheme for a computer system having agents (100) of a pre-emptible bus (4) and a non-pre-emptible bus (6). An agent (110) of the non-pre-emptible bus (6), having a data width capability of N bits, when receiving a grant to write to the pre-emptible bus (4), writes instead to a collection buffer (80) capable of holding a block of more than one N bit data segments. When the collection buffer (80) is filled, the collection buffer (80) writes the entire block of data segments over the pre-emptible bus (4) to a CPU (10) or memory (60) of the computer system. Preferably, the collection buffer (80) is filled when the block size is equal to the data width capability of the pre-emptible bus (4), such that a single write to the pre-emptible bus (4) utilizes the entire capacity of the pre-emptible bus (4) in a given data transaction. Further, where the system has a CPU posting buffer (55), a system lock-up prevention negotiator is provided that drains and disables the CPU posting buffer (55) during the data transaction.

Abstract translation: 一种用于具有可预占总线（4）和不可预先排除总线（6）的代理（100）的计算机系统的收集缓冲方案。 当接收到写入可预占总线（4）的授权时，具有N位的数据宽度能力的不可预先总线（6）的代理（110）代替写入收集缓冲器（80） ）能够保存多于一个N位数据段的块。 当收集缓冲器（80）被填充时，收集缓冲器（80）将整个数据段块写入可预留的总线（4）上，以写入计算机系统的CPU（10）或存储器（60）。 优选地，当块大小等于可预充电总线（4）的数据宽度能力时，收集缓冲器（80）被填充，使得对可预留总线（4）的单个写入利用了 在一个给定的数据交易中的可预见的总线（4）。 此外，在系统具有CPU发布缓冲器（55）的情况下，提供在数据交易期间排出并禁用CPU发布缓冲器（55）的系统锁定防止协商者。

公开(公告)号：WO1997043709A1

公开(公告)日：1997-11-20

申请号：PCT/US1997006295

申请日：1997-04-14

Applicant: INTEL CORPORATION ,  HOFFMAN, Eric, J.

Inventor： INTEL CORPORATION

IPC: G06F07/58

CPC classification number: H04L9/0866 ,  G06F7/588

Abstract: A random number generator using a single, slow, voltage controlled oscillator (10) which receives a noise input (14) and a plurality of high frequency ring oscillators (25-30). The ring oscillators are sampled under control of the slow oscillator. A circuit is used between the output of each of the ring oscillators and its respective D-type latch (31-36) to assure that the sampling is unbiased, that is, that there will be near even distribution of 1s and 0s in the random numbers.

Abstract translation: 一种使用接收噪声输入（14）和多个高频环形振荡器（25-30）的单个，缓慢的压控振荡器（10）的随机数发生器。 环形振荡器在慢振荡器的控制下进行采样。 在每个环形振荡器的输出与其各自的D型锁存器（31-36）之间使用一个电路，以确保采样是无偏的，也就是说，在随机的情况下将存在1s和0s的近均匀分布 数字。

公开(公告)号：WO1997037305A1

公开(公告)日：1997-10-09

申请号：PCT/US1997004905

申请日：1997-03-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  TRAW, C., Brendan, S. ,  HANNAH, Eric, C. ,  HAUCK, Jerrold, V. ,  COULSON, Richard, L. ,  HOSLER, Brad, W.

IPC: G06F11/00

CPC classification number: G06F21/85 ,  G06F21/42 ,  G06F21/55 ,  G06F2211/002 ,  G06F2221/2103 ,  G06F2221/2129

Abstract: Security from an unwanted intrusion into a computer system (12) is provided by coupling a host component (10) with a peripheral component (16-18) using a high-speed serial bus (14.1-14.4) having a high-speed physical layer and using features of the bus (14.1-14.4) to implement the security. In an embodiment, the high-speed serial bus (14.1-14.4) has a secondary bus layer that is used to implement a number of the security features of the invention.

Abstract translation: 通过使用具有高速物理层（14.1-14.4）的高速串行总线（14.1-14.4）将主机组件（10）与外围组件（16-18）耦合，从而防止来自计算机系统（12）的不想要的入侵的安全性 并使用总线（14.1-14.4）的功能实现安全。 在一个实施例中，高速串行总线（14.1-14.4）具有辅助总线层，其用于实现本发明的许多安全特征。

公开(公告)号：WO1997036330A1

公开(公告)日：1997-10-02

申请号：PCT/US1997004686

申请日：1997-03-20

Applicant: INTEL CORPORATION ,  BOHR, Mark, T. ,  GREASON, Jeffrey, K.

Inventor： INTEL CORPORATION

IPC: H01L29/76

CPC classification number: H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

Abstract: A memory cell (50) with vertically stacked crossovers (520, 521). In prior memory cells, crossover connections within the memory cell were implememted in the same device layer. This wasted valuable design space, since the crossovers were therefore required to sit side-by-side in the layout design. The present invention implements crossovers in different materials on different device layers. The crossovers may therefore be vertically stacked on top of each other, reducing the area of the memory cell.

Abstract translation: 具有垂直堆叠的交叉（520,521）的存储单元（50）。 在先前的存储器单元中，存储器单元内的交叉连接在相同的器件层中被实现。 这浪费了宝贵的设计空间，因为交叉路口因此需要在布局设计中并排。 本发明在不同的器件层上实现不同材料的交叉。 因此，交叉可以垂直堆叠在彼此的顶部，从而减小存储单元的面积。

公开(公告)号：WO1997036241A1

公开(公告)日：1997-10-02

申请号：PCT/US1997003569

申请日：1997-03-11

Applicant: INTEL CORPORATION ,  SHIPMAN, Mark, S. ,  CHRISTESON, Orville, H. ,  LABATTE, Timothy, E., W.

Inventor： INTEL CORPORATION

IPC: G06F13/00

CPC classification number: G06F12/1466

Abstract: A method and apparatus for protecting data using lock values in a computer system includes indicating that the computer system does not support locked accesses to the data. However, upon receipt of a request (310) to write to a storage area where the data is contained, the present invention checks (320) whether a lock value corresponding to the request matches a predetermined lock value. If the lock value matches the predetermined lock value, then the data is written to the storage area (330); otherwise, the storage area is left unmodified (340).

Abstract translation: 用于使用计算机系统中的锁值保护数据的方法和装置包括指示计算机系统不支持对数据的锁定访问。 然而，在接收到写入包含数据的存储区域的请求（310）时，本发明检查（320）与该请求相对应的锁定值是否与预定的锁定值相匹配。 如果锁定值与预定的锁定值匹配，则将数据写入存储区域（330）; 否则，存储区域不被修改（340）。

公开(公告)号：WO1997033222A1

公开(公告)日：1997-09-12

申请号：PCT/US1997003522

申请日：1997-03-03

Applicant: INTEL CORPORATION ,  LIN, Derrick, Chu ,  MINOCHA, Punit ,  PELEG, Alexander, D. ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

Inventor： INTEL CORPORATION

IPC: G06F05/01

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: An apparatus for performing a shift operation on a packed data element (901) having multiple values. The apparatus having multiple muxes (910-913), each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represents a shifted packed intermediate result on a first bus (919) is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input (996-999). Each of the multiple bits driven by a correction circuit (932) is coupled to a corresponding select input. Each output (915-918) corresponds to a bit of a shifted packed result.

Abstract translation: 一种用于对具有多个值的压缩数据元素（901）执行移位操作的装置。 具有多个多路复用器（910-913）的装置中，多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。 表示第一总线（919）上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。 表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入（996-999）。 由校正电路（932）驱动的多个比特中的每一个被耦合到对应的选择输入。 每个输出（915-918）对应于移位包装结果的位。

公开(公告)号：WO1997025742A1

公开(公告)日：1997-07-17

申请号：PCT/US1996020865

申请日：1996-12-30

Applicant: INTEL CORPORATION ,  LODER, William, G. ,  McMAHON, John, Francis

Inventor： INTEL CORPORATION

IPC: H01L23/48

CPC classification number: H01L23/49861 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/05553 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/8547 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An electronic package which has a plurality of stacked integrated circuit dies. The package includes a first die (12) that is mounted to a die paddle (16) of a lead frame (18). The first die is also connected to the leads of the lead frame by bond wires (28). A second die (14) is mounted to the top surface of the first die and electrically connected to the first die with bond wires. The first die, second die and die paddle are all enclosed by a package.

Abstract translation: 一种具有多个堆叠集成电路管芯的电子封装。 该包装包括安装到引线框架（18）的管芯（16）的第一管芯（12）。 第一管芯也通过接合线（28）连接到引线框架的引线。 第二管芯（14）安装到第一管芯的顶表面，并用接合线与第一管芯电连接。 第一个模具，第二个模具和裸片均由包装封闭。