Abstract:
A data processing system includes a plurality of stations (412), first and second star couplers (416A, 416B) and first and second pairs of transmission lines (414A, 414B) associated with each station (412). The first pair of transmission lines (414A) is connected between its associated station (412) and the first star coupler (416A) and the second pair of transmission lines (414B) is connected between its associated station (412) and the second star coupler (416B). Each pair of transmission lines includes a first transmission line (418A, 418B) for carrying signals from its associated station (412) and a second transmission line (420A, 420B) for carrying signals to its associated station (412). Each station (412) includes a plurality of subsystems (424A, 424B, 424C), coupled by respective interface circuits (428) to both pairs of transmission lines. The system provides reduced transmission interference and high reliability. The star couplers are preferably optical but may be electrical or magnetic star couplers.
Abstract:
A data processing system (10) includes a plurality of subsystems coupled via respective interface circuits (28) to a pair of transmission lines (18, 20) for carrying messages inrespective directions from and to the subsystems. The transmission lines (18, 20) are interconnected by an optical star coupler (16). The interface circuits (28) include respective error detection circuits arranged to detect errors in every transmitted message. Thus errors may be detected in a transmitted message even if the message is not intended to be received by the subsystem whose associated interface circuit (28) detects an error. For certain detected errors an ABORT signal is produced to cause the erroneous message to be garbled by the superposition of binary "1" signals. The subsystems include circuits which detect when the postamble of a message is garbled.
Abstract:
A power supply includes a digital controller (10) which generates pulse-width modulated control signals for controlling the duty cycles of switching transistors (36) for the purpose of regulating the output voltage of the power supply. The controller (10) incorporates a diagnostic system which includes a plurality of comparators (297) arranged to compare each of a number of voltage level signals representing operating conditions at portions of the power supply with a reference voltage, and logic circuits (330-348) responsive to the outputs of the two comparators for generating an output identifying an element of the power supply which has failed. This output is stored and is displayed in a LED display (154) which is actuated by operation of a switch member (360). Integrated circuit chips may be used in the controller so that the diagnostic system is of simple construction and of low cost.
Abstract:
Customer queue control apparatus for an establishment having a plurality of service stations (40-50) utilizes a main queue and a plurality of local queues having not more than two members, at the individual service stations (40-50). A switch (66) detects the presence of a customer at the head of the main queue and keys (52) at the individual service stations (40-50) are utilized by the operators to signal that the station is open for business or that a customer has left the station after service. A synthesized voice message directs the customer to a local queue determined to have the expected minimum waiting time, dependent on the number of customers in each local queue, and the probable service time per customer in each local queue.
Abstract:
A plasma charge transfer device display system includes input driver circuits (7) coupled to respective input driver lines of a display panel (3) and phase driver circuits (8) coupled to phase driver lines for shifting trapped charge in the panel (3). A power supply (9) provides a toggle voltage V which switches alternately between +140 volts and -60 volts and which is applied to the input driver circuits (7). Control logic (4) causes the voltages on selected ones of the input driver lines to switch from -60 volts to +140 volts simultaneously with the switching of the voltage on the first one of the phase driver lines from +140 volts to zero volts; the resulting large transient voltage changes cause gas discharges. The phase driver line switches back to +140 volts before the input driver line switches back to -60 volts. Trapped charges are progressed along the device in synchronism with switching of the phase drivers (8). The device operates with relatively low absolute magnitude voltages enabling implementation by hybrid or monolithic circuits.
Abstract:
Un generateur de nombres au hasard (10) produit des bits variant au hasard, dans lequel les problemes de polarisation et d'autocorrelation sont reduits dans un circuit (30, 40, 42, 48) couple a un generateur de bruit et a un circuit d'echantillonnage (12, 26). Pour reduire l'autocorrelation, les bits variant au hasard sont stockes dans un premier registre a decalage (30), les bits dans le registre a decalage etant couples a un second registre a decalage (40). Le second registre a decalage (40) est controle dans le temps par un compteur (48) sensible aux bits envoyes au premier registre a decalage de maniere telle que la synchronisation du second registre a decalage n'ait lieu qu'apres rejet d'un certain nombre de bits par le premier registre a decalage. Pour reduire la polarisation, les registres a decalage sont couples par des portes OU EXCLUSIF (42A-42N) et les sorties du second registre a decalage sont couples aux entrees des portes OU EXCLUSIF.
Abstract:
In order to provide fast data transfers and to ensure that the capacitive loading remains fixed, a data communication bus structure for interconnecting a desired number of subsystems of a data processing system comprises an integrated circuit (1) having bus conductors (50, 60, 70) of fixed length and a fixed number of ports (10, 20, 30) for connecting the subsystems. Each port comprises the control and data terminals for a group of driver/receiver circuits (11-13, 21-23, 31-33), each driver/receiver circuit of a group being connected to a respective bus conductor. Each driver/receiver circuit comprises a driver circuit having address and data output latches and driver gates, and a receiver circuit having address and data input latches.
Abstract:
Apparatus and method for ink jet printing in which ink (14) circulated in a continuous moving stream in a closed capillary tube (10) is caused to be deflected at a point inside the circulating ink system by deflecting means (18) arranged to produce pressure pulses to effect a printing operation by deflecting ink from the stream towards a nozzle (20). The deflected ink is ejected through the nozzle (20) in the form of droplets. The velocity (V u) of the ejected droplets depends upon the velocity of the continuously-flowing ink (V u) and on the velocity of the deflection pulse (V u).
Abstract:
A keyboard includes a resilient foam layer (28) having an array of holes (30) therein with the layer (28) being sandwiched between a flexible sheet having dome-shaped areas (34) aligned with said holes and a dielectric member (38), the flexible sheet and dielectric member having electrodes (36, 40) thereon which are arranged to complete a circuit associated with a hole (30) when the flexible sheet and member are moved toward each other. A snap action of the dome-shaped areas (34) in the switch movement provides for improved tactile response and switch travel and reduced switch actuating force. Additional foam layers enhance the operating characteristics of the embodiments. A method of production of the keyboard entails determining the operating parameters of a desired keyboard and selecting the relative density and thicknesses of various resilient layers and flexible sheets in the keyboard to determine the switch actuating force, the extent of travel of the switch, and the location of the "makepoint" of the switch at a position between the start and end of switch travel.
Abstract:
A data processing system including processing elements (22) and a central memory (10) has an input/output system for handling high data flow rates comprising an I/O processor (23) providing serial lines (31) to a plurality of peripheral subsystems (30), the I/O processor comprising a dynamic channel exchange coupling the serial lines to at least one serial channel processor (20). Processor (20) includes arithmetic logic means, a scratch-pad, a buffer for data transfer between the dynamic channel exchange and the central memory, and a control store having a plurality of routines for implementing a method of communication between the I/O processor and the peripheral subsystems. The method of communication involving polling the ith serial channel for a peripheral ready indication, establishing a message exchange for communication if a peripheral ready indication is detected, checking for a processor element request for communication with a peripheral subsystem, and providing a message exchange for an initial communication across the corresponding bit line to the peripheral subsystem.