公开(公告)号：FI861267A0

公开(公告)日：1986-03-25

申请号：FI861267

申请日：1986-03-25

Applicant: RCA CORP

Inventor： WILLIS DONALD HENRY

IPC: H04N3/16 ,  H04N3/27 ,  H04N5/06 ,  H04N5/12 ,  H04N7/01 ,  H04N

Abstract: In a synchronized digital horizontal deflection system operating at 2xf H , a first word (HDPW) is produced that is indicative of the length of one-half the period H between f H rate horizontal sync pulses (Hs). A first f H rate signal (CMa) that is synchronized to the horizontal sync pulses (Hs) is generated. The first f H rate signal (CMa) is time shifted by one-half of the period H, in accordance with the first word (HDPW) to produce a second f H rate signal (CMb). The first (CMa) and second (CMb) signals are multiplexed (in 40) for generating a horizontal deflection control signal (CMa, CMb) at 2xf H rate that controls the retrace interval timing in a deflection circuit output stage (41).

公开(公告)号：DK65086A

公开(公告)日：1986-02-11

申请号：DK65086

申请日：1986-02-11

Applicant: RCA CORP

Inventor： MCDONALD JAMES ALEXANDER ,  WAYBRIGHT GEORGE CLEVELAND ,  WILLIS DONALD HENRY ,  SUTHERLAND II HUGH FERRAR ,  LUZ DAVID WARREN ,  HAFERL PETER EDUARD

IPC: H04N3/23 ,  H01J29/56 ,  H04N3/233 ,  H04N

公开(公告)号：ZA852653B

公开(公告)日：1985-12-24

申请号：ZA852653

申请日：1985-04-10

Applicant: RCA CORP

Inventor： FLING RUSSELL THOMAS ,  WILLIS DONALD HENRY ,  MCNEELY DAVID LOWELL

IPC: H04N5/202 ,  H03G3/00 ,  H03G3/20 ,  H04N9/68 ,  H03K ,  H04N

Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.

公开(公告)号：FI854661A0

公开(公告)日：1985-11-26

申请号：FI854661

申请日：1985-11-26

Applicant: RCA CORP

Inventor： WILLIS DONALD HENRY

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/20 ,  H04N7/26 ,  H04N9/455 ,  H03M

Abstract: a A narrow bandwidth analog-to-digital conversion (ADC) system is described in the context of the color burst processing and burst phase detecting circuitry of a digital color television receiver. The ADC (14) includes a dither generator which adds a dither signal to either the analog input signal (10) or to the reference signal (38) used by the ADC. This dither signal increases in magnitude by 1/16 of an LSB value at a rate one-quarter of the burst frequency and changes in sign at one-half of the burst frequency. This signal passes through a low-pass filter (18) in the chrominance channel providing an increase in sample resolution by averaging the samples in a chroma band-pass filter and in the phase detecting circuitry (30).

公开(公告)号：FI851632L

公开(公告)日：1985-11-03

申请号：FI851632

申请日：1985-04-25

Applicant: RCA CORP

Inventor： STOUGHTON JOHN WILLIAM ,  WILLIS DONALD HENRY

IPC: H04N9/64 ,  H04N11/04 ,  H04N

Abstract: A beam current limiting (BCL) control apparatus for a digital television system includes a control unit (31) for reducing excessive beam currents, by controlling an analog-to-digital control means (3a) for the analog-to-digital converter (ADC) (3), which converts an analog composite video signal, including both luminance and chrominance components, to corresponding digital samples. The analog-to-digital control means (3a) can fulfil its function by controlling the reference voltage for the ADC (3). A switching circuit (33) may be included for preventing the reference voltage from being changed in response to the beam current during horizontal blanking intervals so as to inhibit interference with digital synchronization component detection and automatic chrominance control. A clamping circuit (35) is coupled to the ADC (3) to inhibit the conversion of portions of the composite video signal extending from the black level (0 IRE umts) to the sync tips from being affected by the BCL operation. This inhibits the BCL operation from adversely affecting the reproduction of details in dark portions of an image.

公开(公告)号：DK196085A

公开(公告)日：1985-11-03

申请号：DK196085

申请日：1985-05-01

Applicant: RCA CORP

Inventor： STOUGHTON JOHN WILLIAM ,  WILLIS DONALD HENRY

IPC: H04N9/64 ,  H04N11/04 ,  H04N

Abstract: A beam current limiting (BCL) control apparatus for a digital television system includes a control unit (31) for reducing excessive beam currents, by controlling an analog-to-digital control means (3a) for the analog-to-digital converter (ADC) (3), which converts an analog composite video signal, including both luminance and chrominance components, to corresponding digital samples. The analog-to-digital control means (3a) can fulfil its function by controlling the reference voltage for the ADC (3). A switching circuit (33) may be included for preventing the reference voltage from being changed in response to the beam current during horizontal blanking intervals so as to inhibit interference with digital synchronization component detection and automatic chrominance control. A clamping circuit (35) is coupled to the ADC (3) to inhibit the conversion of portions of the composite video signal extending from the black level (0 IRE umts) to the sync tips from being affected by the BCL operation. This inhibits the BCL operation from adversely affecting the reproduction of details in dark portions of an image.

公开(公告)号：GB2157530A

公开(公告)日：1985-10-23

申请号：GB8509266

申请日：1985-04-11

Applicant: RCA CORP

Inventor： FLING RUSSELL THOMAS ,  WILLIS DONALD HENRY ,  MCNEELY DAVID LOWELL

IPC: H04N5/202 ,  H03G3/00 ,  H03G3/20 ,  H04N9/68 ,  H04N5/52

Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.

公开(公告)号：DE3512996A1

公开(公告)日：1985-10-17

申请号：DE3512996

申请日：1985-04-11

Applicant: RCA CORP

Inventor： FLING RUSSELL THOMAS ,  WILLIS DONALD HENRY ,  MCNEELY DAVID LOWELL

IPC: H04N5/202 ,  H03G3/00 ,  H03G3/20 ,  H04N9/68 ,  H04N5/14

Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.

公开(公告)号：GB2112970B

公开(公告)日：1985-03-27

申请号：GB8300750

申请日：1982-05-26

Applicant: RCA CORP

Inventor： WILLIS DONALD HENRY ,  CLAYBURN RANDALL CROSS

IPC: G03F7/20 ,  G05F3/06 ,  H01F20060101 ,  H01F17/04 ,  H01F17/06 ,  H04N3/18 ,  H01F19/04 ,  H01F27/00 ,  H01F27/42 ,  H01J29/70 ,  H01J29/76 ,  H01J29/98 ,  H04N3/185 ,  G05F1/38

Abstract: The primary of a transformer with a high leakage inductance is coupled to an unregulated alternating voltage source. The output voltage from a secondary winding is full wave rectified by diodes and filtered by a capacitor to provide a voltage for the audio circuits. The voltage developed in another secondary winding is full wave rectified and is filtered by a capacitor to provide a voltage for the tube grid circuits. A separate winding is used to provide the EHT supply. The output windings are tightly coupled magnetically and their output voltages are controlled by a saturable reactor connected to the tube grid supply winding. This reactor comprises a winding on a magnetically saturable core and coupled to a resonating capacitor. A permanent magnet polarises the core to stabilise the output voltages against temp. effects.

公开(公告)号：FI850856A0

公开(公告)日：1985-03-01

申请号：FI850856

申请日：1985-03-01

Applicant: RCA CORP

Inventor： WILLIS DONALD HENRY

IPC: H04N5/59 ,  H04N5/16 ,  H04N9/64 ,  H04N

Abstract: In a digital video signal processing system including an image reproducing kinescope and a digital-to-analog converter (DAC), excessive kinescope beam current are automatically limited in response to a control signal which varies a reference voltage for the DAC such that the peak-to-peak amplitude of analog video signals from the DAC is reduced. A version of the control signal is applied to the output of the DAC with a magnitude and polarity for substantially negating unwanted shifts of the video signal black level during the beam current limiting mode.