公开(公告)号：US09754934B2

公开(公告)日：2017-09-05

申请号：US15383214

申请日：2016-12-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/52 ,  H01L27/06 ,  H01G5/011 ,  H01G5/16 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.

公开(公告)号：US09721858B2

公开(公告)日：2017-08-01

申请号：US14675468

申请日：2015-03-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/522 ,  H01L23/04 ,  H01L49/02 ,  B81B3/00 ,  H01G5/18 ,  H01L27/06

CPC classification number: H01L23/04 ,  B81B3/0021 ,  B81B2201/0221 ,  H01G5/18 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.

公开(公告)号：US09577053B2

公开(公告)日：2017-02-21

申请号：US14963670

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66106 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

Abstract translation: 本公开涉及一种齐纳二极管，其包括在平行于衬底表面的平面上形成在半导体衬底中的齐纳二极管结，并位于具有第一导电类型的阳极区域和具有第二导电类型的阴极区域之间 ，阴极区域从衬底的表面延伸。 第一导电区域被配置为在向第一导电区域施加第一电压时产生垂直于齐纳二极管结的平面的第一电场，并且第二导电区域被配置为沿着第一导电区域的平面生成第二电场 在向第二导电区施加第二电压时的齐纳二极管结。

公开(公告)号：US09490415B2

公开(公告)日：2016-11-08

申请号：US14930204

申请日：2015-11-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L27/16 ,  H01L35/32 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L35/32 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.

公开(公告)号：US20160293540A1

公开(公告)日：2016-10-06

申请号：US14920621

申请日：2015-10-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Sebastian Orellana

IPC: H01L23/522 ,  H01H59/00 ,  H01L23/532

CPC classification number: H01H49/00 ,  H01H59/0009 ,  H01H2001/0052 ,  H01H2001/0057 ,  H01H2001/0078 ,  H01H2061/006 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.

Abstract translation: 为了例如，为了改善位于金属化水平的两个金属片之间的欧姆接触，这两个金属片配备有位于金属化水平处的至少部分地至少部分地在上面的通孔级的两个偏移通孔。 每个偏移通孔包括例如不可氧化或基本上不可氧化的化合物，例如Ti / TiN的阻挡层。

公开(公告)号：US09459157B2

公开(公告)日：2016-10-04

申请号：US14161502

申请日：2014-01-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: G01K7/08 ,  G01N25/18 ,  G01K17/08 ,  G01K13/00 ,  H01H1/00 ,  H01H37/46 ,  H01H37/00

CPC classification number: G01K13/00 ,  H01H1/0036 ,  H01H37/46 ,  H01H2037/008

Abstract: A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold.

Abstract translation: 一种用于监测电路周围温度的装置，包括：电荷存储元件; 充电撤离装置; 以及将所述存储元件连接到所述排气元件的热机械开关，当所述温度超过阈值时，所述开关能够关闭而不使所述电路被电力供电。

公开(公告)号：US20160203917A1

公开(公告)日：2016-07-14

申请号：US15077702

申请日：2016-03-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01G5/16 ,  H01G5/011

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.

Abstract translation: 可变电容器包括设置在覆盖在基板上的第一金属层中的固定主电容器电极，与固定主电容器电极间隔开的第二主电容器电极和设置在与固定主电容器电极相邻的第一金属层中的可移动电容器电极。 可以使可动电容电极处于与固定主电容器电极欧姆电连接的第一位置，使得可变电容器具有第一电容值或与固定主电容器电极间隔开的第二位置，使得可变电容器具有 第二电容值。

公开(公告)号：US20160116631A1

公开(公告)日：2016-04-28

申请号：US14985037

申请日：2015-12-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: G01V7/04 ,  B81C1/00 ,  H01H37/32 ,  H01L29/423 ,  B81B3/00 ,  H01H37/04 ,  H01L21/3213 ,  H01L49/02

CPC classification number: G01V7/04 ,  B81B3/001 ,  B81B2201/018 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0361 ,  B81B2203/04 ,  B81C1/00111 ,  H01H9/02 ,  H01H37/04 ,  H01H37/32 ,  H01H37/42 ,  H01H61/013 ,  H01L21/32139 ,  H01L28/82 ,  H01L28/88 ,  H01L29/4238

Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.

Abstract translation: 公开了一种用于制造集成电路尖锐元件的方法。 元件具有突出部，其凹部朝向元件引导其凹面。 元件包括第一可蚀刻材料。 围绕元件的凹部形成区域。 该区域包括与用于特定蚀刻剂的第一材料不太可蚀刻的第二材料。 用特定的蚀刻剂蚀刻第一材料和第二材料，以在凹部中形成开放的凹坑，从而形成元件的尖锐区域。

公开(公告)号：US20160093609A1

公开(公告)日：2016-03-31

申请号：US14957544

申请日：2015-12-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.

Abstract translation: 提供一种形成具有设置在金属化中的可变电容器的集成电路芯片的方法。 线路金属化的后端形成在半导体衬底上。 可变电容器形成在线金属化后端的腔内。 可变电容器包括设置在线金属化后端的第一金属层中的固定主电容器电极，电连接到线金属化后端的第二金属层并与固定主电容器垂直间隔的第二主电容器电极 电极和设置在与固定主电容器电极相邻的第一金属层中的可动电容电极。

公开(公告)号：US20160033937A1

公开(公告)日：2016-02-04

申请号：US14883364

申请日：2015-10-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: G04F10/10 ,  H01L29/51 ,  G11C16/04 ,  H01L27/115

CPC classification number: G04F10/10 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/349 ,  G11C27/005 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

Abstract translation: EEPROM存储单元包括双栅极MOS晶体管，其中两个栅极被绝缘层隔开。 绝缘层包括具有比第一部分低的绝缘性能的第一部分和第二部分。 第二部分至少部分地位于晶体管的沟道区之上。