公开(公告)号：EP0521483A3

公开(公告)日：1994-01-05

申请号：EP92111148.0

申请日：1992-07-01

Applicant: JAPAN GORE-TEX, INC.

Inventor： Fukutake, Sunao, ,  Wani, Takayuki, ,  Ohashi, Kazuhiko,

IPC: C23C18/20 ,  H05K3/18 ,  H05K3/38 ,  H01L23/14

CPC classification number: H05K3/422 ,  C23C18/208 ,  C23C18/30 ,  H01L21/481 ,  H01L23/145 ,  H01L2924/0002 ,  H05K1/0353 ,  H05K3/386 ,  H05K3/427 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0355 ,  H05K2201/09581 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/3154 ,  H01L2924/00

Abstract: A carrier sheet for printed circuits and semiconductor chips having enhanced adhesion of conductive metal layers to a fluororesin surface resulting from rendering the fluororesin surface hydrophilic by a hydrophilic macromolecule before plating the metal onto the surface.

Abstract translation: 一种用于印刷电路和半导体芯片的载体片，其具有增强的导电金属层对氟树脂表面的粘附力，所述载体片通过在将金属镀覆到表面上之后使亲水性大分子使氟树脂表面亲水化而产生。

公开(公告)号：EP0562187A1

公开(公告)日：1993-09-29

申请号：EP92302521.7

申请日：1992-03-24

Applicant: SANWA LABORATORY LTD.

Inventor： Yamaguchi, Hideaki ,  Kawai, Hideyuki ,  Tachibana, Daikichi ,  Yamaguchi, Kenichi

IPC: H05K3/06 ,  C23F1/02

CPC classification number: H05K3/061 ,  C23F1/02 ,  H05K3/0094 ,  H05K3/427 ,  H05K2201/09581 ,  H05K2203/0582 ,  H05K2203/0591 ,  H05K2203/0769 ,  H05K2203/0786 ,  H05K2203/124

Abstract: Copper through-hole printed wiring boards are produced by forming an etching resist layer on the copper plating of a double sided copper clad laminate. The etching resist layer is formed after a negative resist pattern is applied to both sides of the laminate, and then dipped in a solution containing at least one salt of 2-alkylbenzimidazoles, 2-alkylalkyl-benzimidazoles, 2-phenyl-benzimidazoles and 2-phenyl-alkylbenzimidazoles. After the negative resist pattern is selectively removed with an alkaline aqueous solution, in accordane with the predetermined pattern of the wiring, the exposed copper plating is etched off with an alkali etchant.

Abstract translation: 通过在双面覆铜层压板的镀铜上形成抗蚀剂层来制造铜通孔印刷线路板。 在将抗蚀剂图案施加到层叠体的两面之后形成抗蚀剂层，然后浸入含有2-烷基苯并咪唑，2-烷基烷基 - 苯并咪唑，2-苯基 - 苯并咪唑和2-苯基 - 苯并咪唑的至少一种盐的溶液中， 苯基alkylbenzimidazoles。 在用碱性水溶液选择性除去负的抗蚀剂图案之后，根据布线的预定图案，用碱蚀刻剂蚀刻暴露的镀铜层。

公开(公告)号：EP0393381A3

公开(公告)日：1991-07-03

申请号：EP90105609.3

申请日：1990-03-24

Applicant: International Business Machines Corporation

Inventor： Davis, Charles Robert ,  Goldblatt, Ronald Dean

IPC: H05K3/44 ,  H05K3/00

CPC classification number: B23K26/382 ,  B23K26/389 ,  B23K26/40 ,  B23K2201/35 ,  B23K2203/08 ,  B23K2203/10 ,  B23K2203/12 ,  B23K2203/166 ,  B23K2203/172 ,  B23K2203/18 ,  B23K2203/42 ,  B23K2203/50 ,  B23K2203/52 ,  B23K2203/54 ,  B23K2203/56 ,  H05K1/056 ,  H05K3/445 ,  H05K2201/0129 ,  H05K2201/09581 ,  H05K2203/0278 ,  H05K2203/068 ,  H05K2203/1438

Abstract: Method for pressing a material (6,8,84) into a through-hole (12) or blind-hole (80) in a substrate (10,82). The material (6,8,84) is disposed on the surface of the substrate (10,82). An environment is provided permitting the material (6,8,84) to flow for example by heating the material (6,8,84) to the glass transition temperature or above. Thereafter pressure is applied causing the material (6,8,84) to flow, first coating the sidewall (18,92) of the hole (12,80) and on the continued application of pressure the material flows to completely fill the hole (12,80). The resulting substrate (10,82) can have a substantially planar surface having holes (12,80) with the periphery coated with or completely filled with the material (6,8,84). The material (6,8,84) is preferably a thermoplastic polymeric material such as a polyimide and a perfluorinated polymer.

Abstract translation: 将材料（6,8,84）压入基板（10,82）中的通孔（12）或盲孔（80）中的方法。 材料（6,8,84）设置在基底（10,82）的表面上。 提供允许材料（6,8,84）例如通过将材料（6,8,84）加热至玻璃化转变温度或更高温度而流动的环境。 此后施加压力导致材料（6,8,84）流动，首先涂覆孔（12,80）的侧壁（18,92），并且在继续施加压力时材料流动以完全填充孔（ 12,80）。 所得到的基底（10,82）可以具有基本上平坦的表面，其具有孔（12,80），周边涂有或完全填充材料（6,8,84）。 材料（6,8,84）优选为热塑性聚合材料，例如聚酰亚胺和全氟化聚合物。

公开(公告)号：EP0332561A3

公开(公告)日：1991-05-02

申请号：EP89480029.1

申请日：1989-02-28

Applicant: International Business Machines Corporation

Inventor： Baise, Arnold Ivan ,  Casey, Jon Alfred ,  Clarke, David Richard ,  Divakaruni, Renuka Shastri ,  Dunkel, Werner Ernest ,  Humenik, James Noel ,  Kandetzke, Steven Michael ,  Kirby, Daniel Patrick ,  Knickerbocker, John Ulrich ,  Matts, Amy Trestman ,  Takacs, Mark Anthony ,  Wiggins, Lovell Berry

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/52

CPC classification number: H01L21/4857 ,  C04B41/488 ,  C04B41/4961 ,  C04B2111/00672 ,  C04B2111/00844 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/09581 ,  H05K2203/1147 ,  H05K2203/308 ,  H01L2924/00

Abstract: The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addressed by backfilling the permeable cracks (33) with a flexible material (35). Uniform gaps between the metal (32) and dielectric materials (31) can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.

公开(公告)号：EP0418313A1

公开(公告)日：1991-03-27

申请号：EP89907006.0

申请日：1989-05-11

Applicant: ARIEL ELECTRONICS, INC.

Inventor： ALLEN, G., Graham ,  BATES, Kenneth, N. ,  DEBARDI, Gary, A. ,  ERLEY, Robert, B. ,  HAMADE, Ramzi, F. ,  HORNE, Stephen, J. Seadancer, Berth B12 ,  JACOBS, Thomas, L. ,  NEOGI, Amar ,  PATEL, Manu, C. ,  ROSE, John, E. ,  SCHLOSSER, Mark, S. ,  WARDEN, David, P.

IPC: B41F15 ,  G05D3 ,  H01B1 ,  H01B5 ,  H01B13 ,  H05K1 ,  H05K3

CPC classification number: H05K3/0091 ,  H01B1/22 ,  H05K1/095 ,  H05K3/1241 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2201/0989 ,  H05K2203/0126 ,  H05K2203/0763

Abstract: On a mis au point un appareil, un procédé et un matériau polymérisable permettant de préparer des tracés électroconducteurs sur une plaquette de circuits (627) (fig. 11) utilisant une technologie auxiliaire. On peut isoler individuellement chaque tracé (637, fig. 12a, typique), lesdits tracés étant directement inscrits dans un processus sériel. Ledit appareil comprend un élément d'extrusion (35 et 37), (fig. 1) permettant d'extruder un premier matériau polymérisable, ainsi qu'un support. Le support (21 et 23) est destiné à maintenir ledit élément d'extrusion et la plaquette de circuits (41) à proximité relative, et à produire un mouvement relatif entre l'élément d'extrusion et la plaquette de circuits. Selon le procédé d'invention, le premier matériau polymérisable est extrudé sur un support de substrat de circuits (631), (fig. 12c) le long de chemins présélectionnés afin de former des tracés (637, 639, 641 et 643), puis ledit premier matériau polymérisable est polymérisé, ce matériau étant conducteur après polymérisation. On a mis au point plusieurs modes de réalisation de systèmes d'extrusion ainsi que plusieurs systèmes pour laminer et percer des plaquettes afin de produire plusieurs élaborations de plaquettes de circuits.

公开(公告)号：EP0332561A2

公开(公告)日：1989-09-13

申请号：EP89480029.1

申请日：1989-02-28

Applicant: International Business Machines Corporation

Inventor： Baise, Arnold Ivan ,  Casey, Jon Alfred ,  Clarke, David Richard ,  Divakaruni, Renuka Shastri ,  Dunkel, Werner Ernest ,  Humenik, James Noel ,  Kandetzke, Steven Michael ,  Kirby, Daniel Patrick ,  Knickerbocker, John Ulrich ,  Matts, Amy Trestman ,  Takacs, Mark Anthony ,  Wiggins, Lovell Berry

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/52

CPC classification number: H01L21/4857 ,  C04B41/488 ,  C04B41/4961 ,  C04B2111/00672 ,  C04B2111/00844 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/09581 ,  H05K2203/1147 ,  H05K2203/308 ,  H01L2924/00

Abstract: The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addressed by backfilling the permeable cracks (33) with a flexible material (35). Uniform gaps between the metal (32) and dielectric materials (31) can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.

Abstract translation: 在金属热循环过程中出现的裂纹：电介质半导体封装是由热膨胀系数不匹配造成的。 可以通过用柔性材料（35）回填可渗透裂缝（33）来解决与这种开裂有关的非气密性。 金属（32）和电介质材料（31）之间的均匀间隙可类似地填充柔性材料，以提供应力消除，整体压缩性和包装强度。 此外，可渗透的骨架电介质可以被制造为具有烧结冶金的烧结多层结构，并随后注入柔性的温度稳定的材料以提供气密性和强度。

公开(公告)号：EP0260857A3

公开(公告)日：1988-09-07

申请号：EP87307886

申请日：1987-09-07

Applicant: NEC CORPORATION

Inventor： Inoue, Tatsuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/04

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/5383 ,  H01L2924/0002 ,  H05K1/024 ,  H05K1/0306 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09581 ,  Y10S428/901 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A multilayer wiring substrate wherein a substrate of ceramic material (11) contains a plurality of power supply wiring layers (1) and is formed with first and second through-holes (20,20a). Each of the first through-holes (20) contains a first metal layer (32,33) which is connected to at least one of the power supply wiring layers (12,13). Each of the second through-holes (20a) has a wall surface coated with a layer of a fluoride resin dielectric (21) with a second metal layer (22) formed on the coating. A circuit is supplied with power via the first metal layers and with signals via the second metal layers. The circuit comprises thin film wiring layers (25) formed on the substrate, insulating layers (24) made of an organic material, and electronic circuit elements (not shown). The substrate is made by coating upper and lower surfaces and through-holes of a substrate with a layer of the fluid resin dielectric, removing the coating from the upper and lower surfaces, forming a metal layer in the upper and lower surfaces and on the coating and removing the metal layer except for portions at each end of and within the through-holes.

公开(公告)号：EP0261301A2

公开(公告)日：1988-03-30

申请号：EP87104696.7

申请日：1987-03-30

Applicant: UBE INDUSTRIES, LTD. ,  MEIKO ELECTRONICS CO., LTD.

Inventor： Nakano, Tsunetomo c/o Chiba Laboratories ,  Sakatani, Fumio c/o Chiba Laboratories ,  Kanda, Takeshi ,  Miyazawa, Takeji

IPC: H05K3/42 ,  H05K3/02

CPC classification number: H05K3/061 ,  H05K3/0094 ,  H05K3/427 ,  H05K2201/09581 ,  H05K2203/0582 ,  H05K2203/135

Abstract: A process for the preparation of a circuit-printed board having a plated through-hole com­prising the steps of: processing a board (3) having an elec­troconductive metal layer (2) on both surfaces to form a through-hole (4); plating at least wall (4a) of the through-hole (4) with an electroconductive metal (5); forming a resist layer (6) in the form of a reverse pattern for a desired circuit pattern over both surfaces of the board (3) except at least on the wall of the plated through-hole (4); depositing elec­trically an ionic resinous paint (9) over the plated wall (4a) of the through-hole (4) and an area of the surface of the board (3) where the resist layer (6) is not provided to form a depo­sited resinous paint layer thereon; removing the resist layer (6) to expose the electroconductive layer (5) (2) of the board (3) at the portion under the resist layer; removing the exposed portion of the electroconductive layer (5) (2) by etch­ing; and removing the deposited resinous paint layer (9). The improvement comprises use of a photo-sensitive dry film for the formation of the reverse pattern. Another improvement comprises use of a specific aqueous solution for the removal of the resinous paint layer.

Abstract translation: 在两个表面上的导电性金属层（2）（3），其具有以形成通孔处理的基板（4）;：具有通孔，包括以下步骤镀一种用于电路印刷电路板的制造方法 电镀中的至少壁（4a）的所述通孔（4），在导电性金属（5）; 对于除至少在电镀的通孔的壁在所述板（3）的两个表面上的所希望的电路图案形成在反转图案形式的抗蚀剂层（6）（4）; 过所述通孔（4）和在所述板（3），其中该抗蚀剂层的表面的区域（6）不被提供给形成沉积的镀覆壁（4a）的沉积的离子树脂漆（9），其电 树脂涂料层在其上; 除去抗蚀剂层（6），以暴露导电层（5）（2）的板（3）在抗蚀剂层下的部分; 去除所述导电层（5）通过蚀刻（2）的暴露部分; 并去除所沉积的树脂涂料层（9）。 改进之处包括用于反向图案的形成中使用的光敏干膜的。 另一个改进之处包括使用用于去除树脂涂料层的特定wässrige溶液。

公开(公告)号：EP0239033A1

公开(公告)日：1987-09-30

申请号：EP87104138.0

申请日：1987-03-20

Applicant: Schöffel, Manfred, Dipl.-Ing.

Inventor： Schöffel, Manfred, Dipl.-Ing.

IPC: H05K3/42

CPC classification number: H05K3/061 ,  H05K3/0094 ,  H05K3/427 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2203/0759 ,  H05K2203/1394

Abstract: Schaltungsträgerplatten aus isolierendem Substrat werden zum Aufbau von elektrischen Leitungsanordnungen verwendet und sind auf einer oder beiden Plattenseiten (11, 12) mit einer elektrisch leitfähigen Schicht (13, 14) versehen und weisen eine Mehrzahl durch die Schaltungsträgerplatte (10) hindurchgehende Bohrungen (15) auf. Die Wandungen (16) der Bohrungen sind durch eine elektrisch leitfähige Schicht (17) abgedeckt, die die Schichten (13, 14) elektrisch leitend verbinden. Eine derartige Platte wird in dieser Form in einem festen Verteilungsmuster der Bohrungen (15) hergestellt und anschliessend mit einem Resistmaterial ein-oder beidseitig bedeckt. In einem vom Anwender vorzunehmenden Verfahrensschritt kann dann entsprechend dem Muster des Resistmaterials (18) das Leiterbahnenmuster auf das Resistmaterial (18) übertragen werden, wobei anschliessend in einem Ätzverfahren die übrige elektrisch leitfähige Schicht (13, 14) weggeätzt wird.

Abstract translation: 由绝缘基板构成的电路支撑板用于电导体结构的构造，并且在板的一侧或两侧（11,12）上设置有导电层（13,14），并且具有多个孔 （15）穿过电路支撑板（10）。 孔的壁（16）被导电地连接层（13,14）的导电层（17）覆盖。 这种板以这种形式以孔（15）的固定分布图形式生产，随后在一侧或两侧用抗蚀剂材料涂覆。 在用户要进行的处理步骤中，可以将导体路径图案转印到抗蚀剂材料（18）上，对应于抗蚀剂材料（18）的图案，导电层（13,14）的其余部分 ）在随后的蚀刻工艺中被蚀刻掉。

公开(公告)号：EP0178864A3

公开(公告)日：1987-09-30

申请号：EP85307304

申请日：1985-10-11

Applicant: SHIKOKU CHEMICALS CORPORATION

Inventor： Tsukagoshi, Minoru ,  Nakayama, Takuo ,  Minagawa, Masahiko ,  Yoshida, Shuji

IPC: H05K03/42 ,  C23F01/02 ,  C23F11/14

CPC classification number: C23F11/149 ,  C23C22/52 ,  C23F1/02 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/427 ,  H05K2201/09581 ,  H05K2203/0582 ,  H05K2203/0591 ,  H05K2203/0769 ,  H05K2203/0786 ,  H05K2203/124

Abstract: Disclosed is a process for producing a copper through-hole printed circuit board, which comprises forming a required pattern on a copper-clad laminated plate using a resist ink soluble in an alkaline aqueous solution, immersing the copper-clad laminated plate in an aqueous solution of a salt or an alkylimidazole compound represented by the following general formula
wherein R 2 represents an alkyl group having 5 to 21 carbon atoms, R 4 represents a hydrogen atom or a methyl group, and HA represents an organic or inorganic acid,
to form on the copper surface of the copper-clad laminated plate an etching resist film composed of the alkylimidazole compound, drying the resulting copper-clad laminated plate, and then treating it with an alkaline etching solution.