公开(公告)号：EP1416373A3

公开(公告)日：2005-01-05

申请号：EP03024591.4

申请日：2003-10-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana ,  Verma, Jayesh

IPC: G06F7/06

CPC classification number: G06F5/10

Abstract: The method and apparatus reduce access time in synchronous FIFOs with zero latency overheads. A FIFO buffer comprises FIFO means (301) storing 'n' data words, each 'm' bits wide, having an 'm' bit wide data input terminal. Furthermore, the FIFO buffer includes read data set selection means (303) connected to the data output terminals of the FIFO means and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. Odd read pointer generating means (304) provide the selection input to the data selection means (303) for selecting data at an odd read address of the read data selection means, while even read pointer generating means (305) provide the input for selecting data at an even read address. Multiplexing means (306) coupled to each of the two data output terminals of the read data set selection means select one of its outputs as the final output of the FIFO. State controlling means (310) coupled to the multiplexing means (306) control the selection of the final output and the selection input to the read data set selection means for selecting an odd read address and an even read address.

公开(公告)号：EP1443645A3

公开(公告)日：2004-09-15

申请号：EP03104135.3

申请日：2003-11-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： SAHA, Kaushik ,  MAITI, Srijib Narayan

IPC: H03H17/06

CPC classification number: H03H17/0223 ,  H03H17/06 ,  H03H2017/0298

Abstract: The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Units), multipliers units, data cache, and load/store units sharing a common instruction cache, and multi-port memory, and an assigning means for assigning to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values. A method is also provided for implementing an improved Finite Impulse Response (FIR) filter providing linear scalability using a multiprocessing architecture platform without the need for delay lines.

公开(公告)号：EP1443645A2

公开(公告)日：2004-08-04

申请号：EP03104135.3

申请日：2003-11-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： SAHA, Kaushik ,  MAITI, Srijib Narayan

IPC: H03H17/06

CPC classification number: H03H17/0223 ,  H03H17/06 ,  H03H2017/0298

Abstract: The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Units), multipliers units, data cache, and load/store units sharing a common instruction cache, and multi-port memory, and an assigning means for assigning to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values. A method is also provided for implementing an improved Finite Impulse Response (FIR) filter providing linear scalability using a multiprocessing architecture platform without the need for delay lines.

Abstract translation: 本发明提供了一种改进的有限脉冲响应（FIR）滤波器，其提供线性可扩展性和实现，而不需要延迟线，包括包括多个ALU（算术和逻辑单元），乘法器单元，数据高速缓存和负载/ 共享公共指令高速缓存的存储单元和多端口存储器，以及分配装置，用于向每个可用处理单元分配指定的唯一部分乘积项的计算以及每个计算的部分乘积在指定的输出样本值上的累积。 还提供了一种用于实现改进的有限脉冲响应（FIR）滤波器的方法，其使用多处理架构平台提供线性可扩展性，而不需要延迟线。

公开(公告)号：EP1359588A2

公开(公告)日：2003-11-05

申请号：EP03009612.7

申请日：2003-04-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Nautiyal, Vivek ,  Kumar, Ashish

IPC: G11C8/14

CPC classification number: G11C7/18 ,  G11C8/14

Abstract: An improved multi-wordline memory architecture providing decreased bitline coupling for increased speed and reduced power consumption comprising an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.

Abstract translation: 一种改进的多字线存储器架构，其提供降低的位线耦合以提高速度和降低的功耗，包括用于将相邻位单元连接到不同字线的交错布置，耦合到用于共享相邻位单元的位线的复用布置。

公开(公告)号：EP1324619A2

公开(公告)日：2003-07-02

申请号：EP02022752.6

申请日：2002-10-11

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana, Flat No. 7

IPC: H04N7/62 ,  H04N7/56 ,  H03L7/197 ,  H04N5/12

CPC classification number: H04N21/4305 ,  H03L7/0992 ,  H03L7/181

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values (29) characterized in that controlled clock source means consists of controllable digital Fractional Divider means (2.5) receiving a control value from digital comparator means (2.3) and a clock input from a digital clock synthesizer means (2.8) driven by a fixed oscillator means (2.7).

公开(公告)号：EP3439313A1

公开(公告)日：2019-02-06

申请号：EP17188533.8

申请日：2017-08-30

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Pvt. Ltd.

Inventor： DASGUPTA, Nabarun ,  CHATTERJEE, Subrata ,  SINGH, Hemendra ,  PATHAK, Amit Kumar

IPC: H04N21/61 ,  H04N21/658 ,  H04N21/422 ,  G01W1/00

Abstract: Disclosed herein is a system (e.g. satellite TV, satellite broadband) including a communications connection, with a set top box (58) coupled to the communications connection. A control unit (70) for a receiver (52) is coupled to the communications connection. At least one environmental sensor (51 a, 51b) is configured to generate environmental data about a local environment in which the at least one environmental sensor is located, and to send the environmental data to the control unit (70). The control unit (70) is configured to transmit the environmental data to the set top box over the communications connection. The set top box (58) is configured to process the environmental data. The set top box (58) may send the environmental data to a server f(62) or weather prediction, use in a community weather portal, etc.

公开(公告)号：EP2830221B1

公开(公告)日：2017-02-08

申请号：EP14190037.3

申请日：2007-12-28

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Jain, Abhishek

IPC: H03K19/00 ,  H03K3/287

CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356156

公开(公告)号：EP1653331B1

公开(公告)日：2011-09-21

申请号：EP05110131.9

申请日：2005-10-28

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： DHIMAN, Gaurav ,  KAPOOR, Gaurav

IPC: G06F9/445 ,  G06F1/32

CPC classification number: G06F1/30 ,  G06F1/3203 ,  G06F9/4418

公开(公告)号：EP2348634A1

公开(公告)日：2011-07-27

申请号：EP10197058.0

申请日：2010-12-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Pvt. Ltd.

Inventor： Veggetti, Andrea Mario ,  Jain, Abhishek ,  Rohilla, Pankaj

IPC: H03K3/037 ,  H03K3/356 ,  H03K19/00

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present invention relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop (10) and at least one retention cell (20; 200) connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal (SO), while during low consumption operation of the flip-flop circuit a latch circuit (22; 220) of the retention cell suitable to memorise data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本发明涉及具有数据保留低消耗触发器电路，其包括至少一个触发器（10）和至少一个保持细胞;连接到所述触发器的输出端，并且被配置以便做到（20 200） 触发器电路的正常手术期间，保持小区发送的数据或逻辑状态存在触发器到其自己的输出端（SO）的输出端上，而触发器电路的低消耗手术期间 闩锁电路（22; 220）适合于记忆的数据或逻辑状态对应于本触发器的输出端子上的负载的数据或逻辑状态保持单元的被激活。

公开(公告)号：EP1898630A3

公开(公告)日：2010-04-28

申请号：EP07114687.2

申请日：2007-08-21

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Mohan Sharma, Vivek ,  Kumar Jain, Sheetal

IPC: H04N5/00 ,  H03C1/60 ,  H03D7/16 ,  H04N5/40

CPC classification number: H04N21/2368 ,  H04N5/40 ,  H04N21/2383

Abstract: The present invention provides a digital radio frequency (RF) modulator for providing modulation for base-band TV signals. The RF modulator provides direct conversion of digital base-band audio and video signals to a desired RF channel frequency, without any analogue up conversion. The RF modulator in the present invention includes an audio module, a video module, and a RF converter. The audio module includes a pre-emphasis filter, a multi-stage audio interpolator and a complex frequency modulator to generate frequency modulated (FM) audio signals. The video module includes a complex VSB filter, a group-delay compensation filter and some processing logic to generate a filtered output video signal. The RF converter includes a complex adder, a complex multiplier and a RF interpolator to construct the base band TV signals and to shift the base band TV signals in a frequency domain to the desired RF channel frequency. The exponential video carrier is generated at baseband and has a frequency whose value is in the range of +/-13.5MHz. The RF interpolator includes a zero pad logic followed by a quadrature band pass filter (BPF), and an optional second stage of another zero-pad logic followed by a real band pass filter (BPF). The second stage is optional in the sense that it is required only if the desired RF channel is in the higher VHF band.