公开(公告)号：WO1998003989A1

公开(公告)日：1998-01-29

申请号：PCT/US1997008728

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N. ,  FULFORD, H., Jim, Jr.

IPC: H01L21/336

CPC classification number: H01L29/66583 ,  H01L21/28123

Abstract: A semiconductor fabrication process for fabricating MOS transistors in which dielectric spacer structures are used prior to gate formation to reduce the gate length below the minimum feature size resolvable by the photolithography equipment. A semiconductor substrate having a channel region laterally disposed between a pair of source/drain regions is provided. A dielectric stack is formed on an upper surface of the semiconductor substrate and patterned to expose on upper surface of a spacer region of the semiconductor substrate. The spacer region includes the channel region and peripheral portions of the pair of source/drain regions proximal to the channel region. The patterning of the dielectric stack results in the formation of a pair of opposing sidewalls in the dielectric stack. Thereafter, a pair of first spacer structures are formed on the pair of opposing sidewalls such that the pair of first spacer structures cover or shadow the peripheral portions of the source/drain regions and such that an upper surface of the channel region is exposed. A gate structure is then formed on the upper surface of the channel region. The gate structure is laterally disposed between the pair of first spacer structures. A first dopant species is then introduced into the source/drain regions of the semiconductor substrate.

Abstract translation: 一种用于制造MOS晶体管的半导体制造工艺，其中在栅极形成之前使用电介质间隔物结构以将栅极长度减小到低于由光刻设备可分辨的最小特征尺寸。 提供了具有横向设置在一对源/漏区之间的沟道区的半导体衬底。 在半导体衬底的上表面上形成电介质堆叠并图案化以暴露在半导体衬底的间隔区域的上表面上。 间隔区域包括通道区域和靠近通道区域的一对源极/漏极区域的外围部分。 电介质堆叠的图案化导致在电介质叠层中形成一对相对的侧壁。 此后，在一对相对的侧壁上形成一对第一间隔结构，使得该对第一间隔结构覆盖或遮蔽源极/漏极区的周边部分，并使沟道区域的上表面露出。 然后在沟道区域的上表面上形成栅极结构。 栅极结构横向设置在一对第一间隔结构之间。 然后将第一掺杂剂物质引入到半导体衬底的源极/漏极区域中。

公开(公告)号：WO1998003902A1

公开(公告)日：1998-01-29

申请号：PCT/US1997008894

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASHMORE, Benjamin, Howard, Jr.

IPC: G05F03/26

CPC classification number: G05F3/262 ,  G05F3/245

Abstract: A circuit is presented which can produce a temperature insensitive, constant current value. The constant current source comprises transistor pairs which mirror a temperature dependent current into a node along with another temperature dependent current. The node thereby receives two temperature dependent currents, wherein one is inversely dependent to that of the other. More specifically, one current may increase as temperature increases, whereas the other current decreases as temperature increases. The two currents may thereby be construed to offset one another such that the output of a common node produces a current output which does not change with either an increase or decrease in temperature imputed upon the current source component.

Abstract translation: 提出了可产生温度不敏感，恒定电流值的电路。 恒流源包括晶体管对，其将与温度相关的电流与另一温度相关的电流一起反映到节点中。 因此节点接收两个依赖于温度的电流，其中一个与另一个相反。 更具体地，一个电流可以随着温度升高而增加，而另一个电流随温度升高而降低。 因此，两个电流可以被解释为彼此偏移，使得公共节点的输出产生不随着对当前源组件估计的温度的增加或降低而改变的电流输出。

公开(公告)号：WO1998002803A1

公开(公告)日：1998-01-22

申请号：PCT/US1996011843

申请日：1996-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RAMAGOPAL, H., S. ,  TRAN, Thang, M. ,  PICKETT, James, K.

IPC: G06F09/38

CPC classification number: G06F9/3834 ,  G06F5/065

Abstract: A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Because each storage location may contain either a load or a store memory operation, the number of available storage locations for load memory operations is maximally the number of storage locations in the entire buffer. Similarly, the number of available storage locations for store memory operations is maximally the number of storage locations in the entire buffer. This invention improves use of silicon area for load and store buffers by implementing, in a smaller area, a performance-equivalent alternative to the separate load and store buffer approach previously used in many superscalar microprocessors.

Abstract translation: 提供了一个加载/存储缓冲区，允许加载存储器操作和存储存储器操作存储在其中。 由于每个存储位置可以包含加载或存储存储器操作，所以用于加载存储器操作的可用存储位置的数目最大限度地为整个缓冲器中的存储位置的数量。 类似地，用于存储存储器操作的可用存储位置的数量最大限度地是整个缓冲器中的存储位置的数量。 本发明通过在较小的区域中实现与许多超标量微处理器中先前使用的单独的负载和存储缓冲器方法的性能等效的替代方案来改进硅面积用于负载和存储缓冲器的使用。

公开(公告)号：WO1998000863A1

公开(公告)日：1998-01-08

申请号：PCT/US1997003552

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KEPLER, Nick

IPC: H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/76834 ,  H01L21/76895

Abstract: The invention utilizes two separate LI stack depositions and etches. In the first step, a layer of oxide etch stop (24) and a layer (26) of TEOS oxide are deposited to form a first LI stack. This stac is then contact etched, filled, and polished. A second LI stack is then formed by deposition of a doped silane oxide layer (30) that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop (24), a second layer (26) of undoped TEOS oxide, and a final layer of doped silane oxide (30).

Abstract translation: 本发明利用两个独立的LI堆叠沉积和蚀刻。 在第一步骤中，沉积氧化物蚀刻停止层（24）和TEOS氧化物层（26）以形成第一LI堆叠。 然后将该stac接触刻蚀，填充和抛光。 然后通过沉积接触蚀刻，填充和抛光的掺杂硅烷氧化物层（30）形成第二个LI堆叠。 该方法产生具有第一层氧化物蚀刻停止层（24），未掺杂的TEOS氧化物的第二层（26）和掺杂的硅烷氧化物（30）的最终层的ILD。

公开(公告)号：WO1998000779A1

公开(公告)日：1998-01-08

申请号：PCT/US1997011150

申请日：1997-06-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  IRETON, Mark, A.

IPC: G06F09/318

CPC classification number: G06F9/3808 ,  G06F9/30174 ,  G06F9/3879 ,  G06F9/3885

Abstract: A microprocessor including an instruction translation unit and a storage control unit is provided. The instruction translation unit scans the instructions to be executed by the microprocessor. The instructions are coded in the instruction set of a CPU core included within the microprocessor. The instruction translation unit detects code sequences which may be more efficiently executed in a DSP core included within the microprocessor, and translates detected code sequences into one or more DSP instructions. The instruction translation unit conveys the translated code sequences to a storage control unit. The storage control unit stores the code sequences along with the address of the original code sequences. As instructions are fetched, the storage control unit is searched. If a translated code sequence is stored for the instructions being fetched, the translated code sequence is substituted for the code sequence.

Abstract translation: 提供了包括指令转换单元和存储控制单元的微处理器。 指令转换单元扫描要由微处理器执行的指令。 指令在包含在微处理器内的CPU核心的指令集中编码。 指令转换单元检测可以在包括在微处理器内的DSP核心中更有效地执行的代码序列，并将检测到的代码序列转换成一个或多个DSP指令。 指令转换单元将转换的代码序列传送到存储控制单元。 存储控制单元将代码序列与原始代码序列的地址一起存储。 当指令被取出时，搜索存储控制单元。 如果为所取指令存储了经翻译的代码序列，则转换后的代码序列代替代码序列。

公开(公告)号：WO1997048209A1

公开(公告)日：1997-12-18

申请号：PCT/US1997000858

申请日：1997-01-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KALKUNTE, Mohan ,  KADAMBI, Jayant ,  MANGIN, James, Laurance ,  KRISHNA, Gopal

IPC: H04L12/413

CPC classification number: H04L12/40163 ,  H04L12/40013 ,  H04L12/40136 ,  H04L12/413

Abstract: Delay times are modified in Ethernet network devices by adding an integer multiple of a delay interval to the minimum interpacket gap (IPG) interval, and decrementing the integer in each network station in response to detected activity on the media. Each station has a unique integer value from the range of zero to the number of stations (N) minus one. The unique integer value ensures that each station has a different delay interval in accessing the media after sensing deassertion of the receive carrier. The station having a zero integer value will have its integer counter reset to (N-1) after a station transmits a data packet on the network, and the stations having nonzero integer values decrement their respective integer counters. Each network station also includes a deferral timer that counts the maximum delay interval of (N-1) delay intervals plus the minimum IPG value, and thus establishes a bounded access latency for a half-duplex shared network.

Abstract translation: 通过将延迟间隔的整数倍添加到最小分组间隙（IPG）间隔，在以太网网络设备中修改延迟时间，并且响应于媒体上检测到的活动而递减每个网络站中的整数。 每个站具有从零到站数（N）减一的唯一整数值​​。 唯一的整数值确保每个站在感测到接收载波的取消消息之后在访问媒体时具有不同的延迟时间间隔。 在站点在网络上发送数据包之后，具有零整数值的站将其整数计数器重置为（N-1），并且具有非零整数值的站减少它们各自的整数计数器。 每个网络站还包括延迟定时器，其计数（N-1）个延迟间隔的最大延迟间隔加上最小IPG值，从而建立半双工共享网络的有界访问等待时间。

公开(公告)号：WO1997047033A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001856

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHEN, Lewis

IPC: H01L21/768

CPC classification number: H01L21/32136 ,  H01L21/76838

Abstract: The high density plasma metal etch rate of a conductive material within a dense array of conductive lines is increased to no less than the etch rate of the conductive material in a bordering open field by injecting a sufficient amount of nitrogen into the total gas flow of the plasma. The injection of nitrogen in amounts of about 15 % and 50 % by volume of the total gas flow effectively reduces the etch rate differential between the dense array and open field, thereby reducing overetching, resist loss, and oxide loss in the open field, and facilitating planarization.

Abstract translation: 导电材料密集阵列内的导电材料的高密度等离子体金属蚀刻速率通过将足够量的氮注入到全部气体流中而增加到不低于边界开放场中导电材料的蚀刻速率 等离子体。 以总气体流量的约15％和50体积％的量注入氮气有效地降低了致密阵列和开放场之间的蚀刻速率差异，从而减少了开放场中的过蚀刻，抗蚀剂损失和氧化物损失，以及 促进平面化。

公开(公告)号：WO1997045985A1

公开(公告)日：1997-12-04

申请号：PCT/US1997001333

申请日：1997-01-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KADAMBI, Jayant ,  KALKUNTE, Mohan ,  MANGIN, James

IPC: H04L12/413

CPC classification number: H04L12/413

Abstract: Efficient communication in a network having a minimum data transmission time interval wherein a data packet is transmitted beginning at a start (t20) of the minimum data transmission time interval. An end (t26) of the minimum data transmission time interval is determined and then at least one next data packet is transmitted after the data packet if the end of the minimum data transmission time (t26) is after the end of the data packet (t21).

Abstract translation: 在具有最小数据传输时间间隔的网络中的有效通信，其中从最小数据传输时间间隔的开始（t20）开始发送数据分组。 确定最小数据传输时间间隔的结束（t26），并且如果最小数据传输时间（t26）的结束是在数据分组结束之后（t21），则在数据分组之后发送至少一个下一个数据分组 ）。

公开(公告)号：WO1997045984A1

公开(公告)日：1997-12-04

申请号：PCT/US1997000876

申请日：1997-01-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KALKUNTE, Mohan ,  MANGIN, James, Laurance

IPC: H04L12/413

CPC classification number: H04L12/413

Abstract: Delay times are modified in Ethernet network devices by adding a slot time to the minimum interpacked gap (IPG) interval between uninterrupted consecutive transmissions by a network station. If a network station transmits a data packet and has another data packet to send, modified delay time prevents the station from contending for access of the media, enabling other stations having data to transmit to attempt access on the media. If a collision occurs during the transmission of a second successive data packet, the network station uses a modified collision arbitration and automatically sets the collision delay interval to zero for the first access attempt. If another collision occurs during the access attempt, the collision interval is calculated according to the truncated binary exponential backoff algorithm.

Abstract translation: 通过将时隙时间添加到网络站的不间断连续传输之间的最小间隔间隔（IPG）间隔，在以太网网络设备中修改延迟时间。 如果网络台发送数据包并发送另一个数据包，则修改的延迟时间将阻止该站争取访问媒体，使能够传送数据的其他站尝试访问媒体。 如果在传送第二连续数据分组期间发生冲突，则网络站使用经修改的冲突仲裁，并且对于第一次访问尝试自动将冲突延迟间隔设置为零。 如果在访问尝试期间发生另一次冲突，则根据截断的二进制指数退避算法计算冲突间隔。

公开(公告)号：WO1997044739A1

公开(公告)日：1997-11-27

申请号：PCT/US1997000891

申请日：1997-01-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LEE, Sherman ,  HALLIGAN, JoAnne, K.

IPC: G06F13/40

CPC classification number: G06F7/768 ,  G06F13/4013

Abstract: A byte swapping device includes first and second data ports and data path logic coupled between the first and second data ports. The byte swapping device is employed in a data processing system comprising a data storage device configured to store bytes of data, a processor which reads data from the data storage device and writes data to the data storage device, and the bytes wapping device coupled between the data storage device and the processor. The first data port is coupled to the storage device and the second data port is coupled to the processor. The storage device is typically a system memory or peripheral device controller. The processor processes data in a first endian format, i.e., big-endian or little-endian format, and at least a portion of the data stored in the data storage device is in the opposite byte ordering. The byte swapping device selectively byte swaps data transferred between the processor and storage device. In the preferred embodiment, data conversion apertures, or ranges, are defined in the processor address space and the processor provides address signals to the byte swapping device. The byte swapping device selectively byte swaps the data based upon the relationship between the addresses received by the byte swapping device and the data conversion apertures. In one embodiment, the processor programs aperture storage elements with the values of the data conversion apertures. In another embodiment, the data conversion apertures are fixed. In an alternate embodiment, the processor provides control signals to the byte swapping device, wherein the byte swapping device selectively converts the data in response to the control signals from the processor. In one embodiment, the processor is configured to execute a characteristic instruction set, wherein the processor provides the one or more control signals to the byte swapping device in response device in response to which instruction in the instruction set the processor executes.

Abstract translation: 字节交换设备包括耦合在第一和第二数据端口之间的第一和第二数据端口和数据路径逻辑。 字符交换装置用于数据处理系统，该数据处理系统包括被配置为存储数据字节的数据存储装置，从数据存储装置读取数据并将数据写入数据存储装置的处理器，以及耦合在数据存储装置 数据存储设备和处理器。 第一数据端口耦合到存储设备，第二数据端口耦合到处理器。 存储设备通常是系统存储器或外围设备控制器。 处理器以第一端格式（即大端或小端格式）处理数据，并且存储在数据存储设备中的数据的至少一部分处于相反的字节排序中。 字节交换设备选择性地交换在处理器和存储设备之间传送的数据。 在优选实施例中，在处理器地址空间中定义数据转换孔径或范围，并且处理器向字节交换设备提供地址信号。 字节交换设备根据由字节交换设备接收的地址与数据转换孔之间的关系，选择性地对数据进行交换。 在一个实施例中，处理器利用数据转换孔径的值来编程孔径存储元件。 在另一个实施例中，数据转换孔是固定的。 在替代实施例中，处理器向字节交换设备提供控制信号，其中字节交换设备响应于来自处理器的控制信号选择性地转换数据。 在一个实施例中，处理器被配置为执行特征指令集，其中响应于处理器执行指令集中的哪个指令，处理器将响应装置中的一个或多个控制信号提供给字节交换装置。