公开(公告)号：US20200220017A1

公开(公告)日：2020-07-09

申请号：US16631363

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Nancy Zelick ,  Harold Kennel ,  Nicholas G. Minutillo ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.

公开(公告)号：US20200098757A1

公开(公告)日：2020-03-26

申请号：US16139684

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew Metz ,  Gilbert Dewey ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/207 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

公开(公告)号：US20200098756A1

公开(公告)日：2020-03-26

申请号：US16138356

申请日：2018-09-21

Applicant: INTEL CORPORATION

Inventor： Aaron Lilak ,  Stephen Cea ,  Gilbert Dewey ,  Willy Rachmady ,  Roza Kotlyar ,  Rishabh Mehandru ,  Sean Ma ,  Ehren Mannebach ,  Anh Phan ,  Cheng-Ying Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238

Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.

公开(公告)号：US20200006510A1

公开(公告)日：2020-01-02

申请号：US16490866

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Sean T. Ma ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Harold W. Kennel ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66

Abstract: In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having corners and thereby reduce leakage current in the transistor. In one embodiment, the non-vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non-vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.

公开(公告)号：US20190189753A1

公开(公告)日：2019-06-20

申请号：US16326663

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Matthew Metz ,  Gilbert Dewey ,  Harold W. Kennel ,  Cheng-Ying Huang ,  Sean T. Ma ,  Willy Rachmady

IPC: H01L29/12 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/122 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/20

Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.

公开(公告)号：US20250031362A1

公开(公告)日：2025-01-23

申请号：US18907358

申请日：2024-10-04

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L21/683 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

公开(公告)号：US12148806B2

公开(公告)日：2024-11-19

申请号：US18408346

申请日：2024-01-09

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey

IPC: H01L29/417

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

公开(公告)号：US12068319B2

公开(公告)日：2024-08-20

申请号：US16141000

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28194 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66537 ,  H01L29/6659

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US11996408B2

公开(公告)日：2024-05-28

申请号：US17726412

申请日：2022-04-21

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Stephanie A. Bojarski ,  Gilbert Dewey ,  Orb Acton ,  Willy Rachmady

IPC: H01L27/088 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/76283 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/785

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

公开(公告)号：US20240136277A1

公开(公告)日：2024-04-25

申请号：US18395192

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/76251 ,  H01L21/76804 ,  H01L27/1203

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.