公开(公告)号：NO20054567L

公开(公告)日：2005-10-04

申请号：NO20054567

申请日：2005-10-04

Applicant: INTERDIGITAL TECH CORP

Inventor： REZNIK ALEXANDER ,  HEPLER EDWARD L ,  MEYER JAN ,  BOHNHOFF PETER ,  HACKETT WILLIAM C ,  FERRANTE STEVEN

IPC: G09G3/28 ,  H04B1/707 ,  H04B7/08 ,  H04B17/00 ,  H04J3/06 ,  H04L25/02 ,  H04B7/216

Abstract: A method and apparatus for processing received wireless communications are provided. Power delay profiles (PDPs) including PDP elements are processed. Less than half of the PDP elements of each PDP are selected. The selected PDP elements are combined based on position, and the combined PDP elements are qualified for further signal processing to determine a received signal path associated with the PDP.

公开(公告)号：AU2005203604A1

公开(公告)日：2005-09-01

申请号：AU2005203604

申请日：2005-08-11

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L

IPC: H04L27/30

公开(公告)号：NO20044923L

公开(公告)日：2005-01-05

申请号：NO20044923

申请日：2004-11-11

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  STARSINIC MICHAEL F ,  LEVI ALAN M ,  BASS DAVID S ,  DESAI BINISH

IPC: H04B1/40 ,  H04B1/707 ,  H04J1/00 ,  H04B7/26 ,  H04J3/00 ,  H04J4/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02 ,  G06F13/00

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

公开(公告)号：CA2516689A1

公开(公告)日：2004-09-10

申请号：CA2516689

申请日：2004-02-18

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  REZNIK ALEXANDER

IPC: H04B1/707 ,  H04L1/00 ,  H04L1/18 ,  H04Q7/32 ,  H04Q7/36 ,  H04B1/69

Abstract: Components and method are provided to efficiently process wireless communications data where prior knowledge of a specific format of the communication data is not available. A wireless transmit receive unit (WTRU) is configured for use in a wireless communication system where communication data for selected channels is transmitted in system time frames in formats selected from among a set of predefined formats. The WTRU has a receiver, a memory, a received chip rate processor (RCRP) and a format detector. The RCRP is preferably configured to despread each wireless signal of spread data received in each time frame using a minimum spreading code or other appropriate key sequence and to store resultant despread data for each respective time frame in the memory. The format detector is preferably configured to determine the number of physical channels and the respective spreading factor for each physical channel for the wireless signal of spread data.

公开(公告)号：BR0212645A

公开(公告)日：2004-08-24

申请号：BR0212645

申请日：2002-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45 ,  G06N5/04

Abstract: The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).

公开(公告)号：NO20041357L

公开(公告)日：2004-04-01

申请号：NO20041357

申请日：2004-04-01

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/39 ,  H03M13/45 ,  G06N5/04

Abstract: The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).

公开(公告)号：AU2003239137A8

公开(公告)日：2003-10-27

申请号：AU2003239137

申请日：2003-04-11

Applicant: INTERDIGITAL TECH CORP

Inventor： BERGHIUS TIMOTHY ,  KOCH MICHAEL ,  REZNIK ALEXANDER ,  MEYER JAN ,  HACKETT WILLIAM C ,  FERRANTE STEVEN ,  HEPLER EDWARD L ,  KAEWELL JOHN DAVID JR ,  BOHNHOFF PETER ,  BASS DAVID S

IPC: H04B1/709 ,  H04B1/10 ,  H04B1/707 ,  H04B7/04 ,  H04B7/08 ,  H04B7/216 ,  H04B7/26 ,  H04L27/06 ,  H04Q7/30 ,  H04B1/69

公开(公告)号：CA2480486A1

公开(公告)日：2003-10-23

申请号：CA2480486

申请日：2003-04-11

Applicant: INTERDIGITAL TECH CORP

Inventor： FERRANTE STEVEN ,  KOCH MICHAEL ,  HACKETT WILLIAM C ,  REZNIK ALEXANDER ,  HEPLER EDWARD L ,  KAEWELL JOHN DAVID JR ,  MEYER JAN ,  BOHNHOFF PETER ,  BASS DAVID S ,  BERGHUIS TIMOTHY

IPC: H04B1/709 ,  H04B1/10 ,  H04B1/707 ,  H04B7/04 ,  H04B7/08 ,  H04B7/216 ,  H04B7/26 ,  H04L27/06 ,  H04Q7/30 ,  H04B1/69 ,  H03K5/01 ,  H04Q7/00

Abstract: A Node-B/base station comprises a plurality of antennas (28I - 28M) for receiving user signals and a path searcher. The path searcher comprises a se t of correlators (42-1, 42-2 ~ 42-P). Each correlator of the set of correlator s correlates an inputted user code with an inputted antenna output. An antenna controller selectively couples an output of one of the plurality of antennas to an input of each.

公开(公告)号：CA2443653A1

公开(公告)日：2002-10-17

申请号：CA2443653

申请日：2002-04-05

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L

IPC: G06F1/025 ,  H03M7/00 ,  H04J11/00 ,  H04J13/00 ,  H04J13/12 ,  H04L20060101 ,  H04L9/00 ,  H04L27/30

Abstract: A system for generating pseudorandom codes using a register (20) which contains an identification of the code tree leg of the desired code and a counter (12) which outputs a successive binary sequence. The output from the counter (12) is bit-by-bit ANDed (18) with the output of the register (20), and those outputs are XORed (22) together to output a single bit. As the counter (12) is sequenced, each count results in a different bit that is output from the XOR gate (22), resulting in the desired code.