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公开(公告)号：WO2009052494A3
公开(公告)日：2009-06-04
申请号：PCT/US2008080500
申请日：2008-10-20
Applicant: INTERDIGITAL TECH CORP , CASTOR DOUGLAS R , HEPLER EDWARD L , STARSINIC MICHAEL F , HACKETT WILLIAM C , BASS DAVID S , GREDONE JOSEPH W , RUSSELL PAUL L JR , GORMAN RICHARD P
Inventor： CASTOR DOUGLAS R , HEPLER EDWARD L , STARSINIC MICHAEL F , HACKETT WILLIAM C , BASS DAVID S , GREDONE JOSEPH W , RUSSELL PAUL L JR , GORMAN RICHARD P
CPC classification number: G06F1/325 , G06F1/3215 , G06F1/3278 , G06F1/3287 , H04W52/00 , H04W52/02 , Y02D10/157 , Y02D10/171 , Y02D70/12 , Y02D70/124 , Y02D70/20
Abstract: A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators.
Abstract translation: 用于优化用于高数据速率应用的调制解调器的方法和装置包括被配置为执行数据处理功能的多个硬件加速器，其中硬件加速器被参数化，处理器被配置为根据期望的功能选择性地激活加速器， 节省功率需求和配置用于在多个硬件加速器之间进行通信的共享存储器。
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2.发明公开SOFTWARE PARAMETERIZABLE CONTROL BLOCKS FOR USE IN PHYSICAL LAYER PROCESSING 有权软件参数控制块FOR USE物理层的处理
公开(公告)号：EP1495567A4
公开(公告)日：2005-05-04
申请号：EP03719734
申请日：2003-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor： HEPLER EDWARD L , STARSINIC MICHAEL F , BASS DAVID S , DESAI BINISH , LEVI ALAN M , MCCLELLAN GEORGE W , CASTOR DOUGLAS R
IPC: H04J1/00 , H04B1/40 , H04B1/707 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02
CPC classification number: H04W88/06 , H04B1/0067 , H04B1/406 , H04B1/707 , H04B7/2618 , H04B2201/70707 , H04L1/0061 , H04L1/0068 , H04L1/0071 , H04L1/08 , H04L2001/0094 , H04W28/18 , H04W74/02 , H04W80/00
Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (303, 307), a composite channel processing block (305, 309) and a chip rate processing block (301, 311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
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公开(公告)号：EP1423823A4
公开(公告)日：2006-03-22
申请号：EP02797883
申请日：2002-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor： HEPLER EDWARD L , STARSINIC MICHAEL F
CPC classification number: H03M13/3905 , H03M13/3972 , H03M13/6505
Abstract: The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).
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公开(公告)号：NO20041357A
公开(公告)日：2004-04-01
申请号：NO20041357
申请日：2004-04-01
Applicant: INTERDIGITAL TECH CORP
Inventor： HEPLER EDWARD L , STARSINIC MICHAEL F
CPC classification number: H03M13/3905 , H03M13/3972 , H03M13/6505
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公开(公告)号：AU2003223595A8
公开(公告)日：2003-11-03
申请号：AU2003223595
申请日：2003-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor： BASS DAVID S , CASTOR DOUGLAS R , MCCLELLAN GEORGE W , LEVI ALAN M , DESAI BINISH , HEPLER EDWARD L , STARSINIC MICHAEL F
IPC: H04J1/00 , H04B1/40 , H04B1/707 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02
Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
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Patent Agency Ranking
公开(公告)号：DE60233236D1
公开(公告)日：2009-09-17
申请号：DE60233236
申请日：2002-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor： HEPLER EDWARD L , STARSINIC MICHAEL F
Abstract: The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).
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公开(公告)号：HK1068436A1
公开(公告)日：2005-04-29
申请号：HK05100601
申请日：2005-01-21
Applicant: INTERDIGITAL TECH CORP
Inventor： HEPLER EDWARD L , STARSINIC MICHAEL F
IPC: G06F11/10 , H03M13/29 , G06N20060101 , H03M13/39 , H03M13/45
Abstract: The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).
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公开(公告)号：CA2459383A1
公开(公告)日：2003-03-20
申请号：CA2459383
申请日：2002-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor： HEPLER EDWARD L , STARSINIC MICHAEL F
Abstract: The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metri cs have been calculated for the first sliding window of the decoder, the revers e metrics for each window are calculated while the forward metrics for the nex t window are calculated. As each new forward metric is calculated and stored into memory (14), the forward metric from the previous window is read from memory (14) for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic val ue is read from memory on the same clock edge that the new forward metric is written to the same memory location. Although this architecture was develope d for a turbo decoder, all convolution codes can use the MAP algorithm of the present inventioon.
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公开(公告)号：NO20044923A
公开(公告)日：2005-01-05
申请号：NO20044923
申请日：2004-11-11
Applicant: INTERDIGITAL TECH CORP
Inventor： HEPLER EDWARD L , CASTOR DOUGLAS R , MCCLELLAN GEORGE W , STARSINIC MICHAEL F , LEVI ALAN M , BASS DAVID S , DESAI BINISH
IPC: H04J1/00 , H04B1/40 , H04B1/707 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02 , G06F13/00
CPC classification number: H04W88/06 , H04B1/0067 , H04B1/406 , H04B1/707 , H04B7/2618 , H04B2201/70707 , H04L1/0061 , H04L1/0068 , H04L1/0071 , H04L1/08 , H04L2001/0094 , H04W28/18 , H04W74/02 , H04W80/00
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公开(公告)号：HK1060493A2
公开(公告)日：2004-07-09
申请号：HK03102741
申请日：2003-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor： BASS DAVID S , CASTOR DOUGLAS R , MCCLELLAN GEORGE W , LEVI ALAN M , DESAI BINISH , HEPLER EDWARD L , STARSINIC MICHAEL F
IPC: H04J1/00 , H04B1/40 , H04B1/707 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02 , H04B , H04Q
Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
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