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    METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK
    1.
    发明申请
    METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK 审中-公开
    用于高效分配存储在存储堆栈中的交互数据的方法和装置

    公开(公告)号：WO2005114865A3

    公开(公告)日：2006-10-12

    申请号：PCT/US2005015173

    申请日：2005-05-03

    Applicant: INTERDIGITAL TECH CORP ,  MCCLELLAN GEORGE W ,  CASTOR DOUGLAS R ,  LEVI ALAN M ,  DESAI BINISH P

    Inventor： CASTOR DOUGLAS R ,  LEVI ALAN M ,  DESAI BINISH P

    IPC: H03M7/00 ,  H04B7/00 ,  H04B7/216 ,  H04J1/00 ,  H04J3/00 ,  H04L12/56 ,  H04W28/14

    CPC classification number: H04L47/14 ,  H04L47/50 ,  H04L47/564 ,  H04L47/621 ,  H04W28/14

    Abstract: A method and apparatus (10) for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor (22) and a memory (12) including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

    Abstract translation: 一种用于有效地分配和释放存储在存储器堆栈中的交织数据的方法和装置（10）。 该装置包括处理器（22）和包括至少一个存储器堆栈的存储器（12）。 处理器接收和交织多个数据块。 为特定传输信道（TrCH）分配每个数据块，并具有指定的传输定时间隔（TTI）。 处理器基于每个数据块的TTI将交织的数据块存储在存储器堆栈中，使得具有较大TTI的数据块较早地分配给存储器堆栈，并且比具有较小TTI的数据块更早地从堆栈中释放 。 在一个实施例中，存储器包括用于公共/共享上行链路信道的第一存储器堆栈，用于专用上行链路信道的第二存储器堆栈，用于公共/共享下行链路信道的第三存储器堆栈以及用于专用下行链路信道的第四存储器堆栈。

    METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK
    2.
    发明专利
    METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK 未知

    公开(公告)号：CA2566263A1

    公开(公告)日：2005-12-01

    申请号：CA2566263

    申请日：2005-05-03

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  LEVI ALAN M ,  DESAI BINISH P ,  MCCLELLAN GEORGE W

    IPC: H03M7/00 ,  H04B7/00 ,  H04B7/216 ,  H04J1/00 ,  H04J3/00 ,  H04L12/56 ,  H04W28/14

    Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

    METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK
    3.
    发明公开
    METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK 审中-公开
    VERFAHREN UND VORRICHTUNG ZUM EFFIZIENTEN ZUTEILEN UND NEUZUTEILEN VON IN EINEM SPEICHERSTAPEL GESPEICHERTEN VERSCHACHTELTEN DATEN

    公开(公告)号：EP1751872A4

    公开(公告)日：2007-06-20

    申请号：EP05745695

    申请日：2005-05-03

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  LEVI ALAN M ,  DESAI BINISH P ,  MCCLELLAN GEORGE W

    IPC: H03M7/00 ,  H04B7/00 ,  H04B7/216 ,  H04J1/00 ,  H04J3/00 ,  H04L12/56 ,  H04W28/14

    CPC classification number: H04L47/14 ,  H04L47/50 ,  H04L47/564 ,  H04L47/621 ,  H04W28/14

    Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

    Abstract translation: 一种用于有效地分配和解除分配存储在存储器栈中的交织数据的方法和设备（10）。 该装置包括处理器（22）和包括至少一个存储器堆栈的存储器（12）。 处理器接收并交织多个数据块。 每个数据块被分配给特定的传输信道（TrCH）并具有指定的传输时间间隔（TTI）。 处理器基于每个数据块的TTI将交织的数据块存储在存储器堆栈中，使得具有较大TTI的数据块较早地分配给存储器堆栈并且比堆栈中从具有较小TTI的数据块更晚释放 。 在一个实施例中，存储器包括用于公共/共享上行链路信道的第一存储器栈，用于专用上行链路信道的第二存储器栈，用于公共/共享下行链路信道的第三存储器栈以及用于专用下行链路信道的第四存储器栈。

    6.
    发明专利
    未知

    公开(公告)号：NO20065601A

    公开(公告)日：2007-01-31

    申请号：NO20065601

    申请日：2006-12-05

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  LEVI ALAN M ,  DESAI BINISH P

    IPC: H04L12/66 ,  H04B7/00 ,  H04J11/00 ,  H04L12/56 ,  H04W28/14

    CPC classification number: H04L47/14 ,  H04L47/50 ,  H04L47/564 ,  H04L47/621 ,  H04W28/14

    Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

    7.
    发明专利
    未知

    公开(公告)号：AT325496T

    公开(公告)日：2006-06-15

    申请号：AT03728300

    申请日：2003-03-27

    Applicant: INTERDIGITAL TECH CORP

    Inventor： KEARNEY KENNETH P ,  MCCLELLAN GEORGE W ,  DRUMMOND RYAN ERIC ,  LEVI ALAN M

    IPC: H04L29/08 ,  H04W52/02 ,  H04W68/00 ,  H04W68/02 ,  H04W80/00 ,  H04W88/02 ,  H04M1/00 ,  H04Q7/38

    Abstract: A wireless communication system implements wireless communications between a base station and a plurality of User Equipments (UEs) including paging of UEs by initially processing paging indicator information. A first embodiment involves a UE's physical layer L1 being configured for interpreting a paging indicator (PI) to activate a preset decoding configuration to process paging data in a pre-specified paging channel (PCH). A second embodiment involves the physical layer control of a next higher level, L2, interpreting the paging indicator and configuring the physical layer L1 to process paging data in a pre-specified PCH.

    9.
    发明专利
    未知

    公开(公告)号：DE60327954D1

    公开(公告)日：2009-07-23

    申请号：DE60327954

    申请日：2003-03-27

    Applicant: INTERDIGITAL TECH CORP

    Inventor： KEARNEYS KENNETH P ,  MCCLELLAN GEORGE W ,  DRUMMOND RYAN ERIC ,  LEVI ALAN M

    IPC: H04W68/02 ,  H04L29/08 ,  H04W52/02 ,  H04W68/00 ,  H04W80/00 ,  H04W88/02

    Abstract: A wireless communication system implements wireless communications between a base station and a plurality of User Equipments (UEs) including paging of UEs by initially processing paging indicator information. A first embodiment involves a UE's physical layer L1 being configured for interpreting a paging indicator (PI) to activate a preset decoding configuration to process paging data in a pre-specified paging channel (PCH). A second embodiment involves the physical layer control of a next higher level, L2, interpreting the paging indicator and configuring the physical layer L1 to process paging data in a pre-specified PCH.

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