公开(公告)号：US20220093586A1

公开(公告)日：2022-03-24

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11164974B2

公开(公告)日：2021-11-02

申请号：US16631363

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Nancy Zelick ,  Harold Kennel ,  Nicholas G. Minutillo ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/201 ,  H01L21/8234 ,  H01L27/088

Abstract: A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.

公开(公告)号：US11164747B2

公开(公告)日：2021-11-02

申请号：US16629550

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Gilbert Dewey ,  Willy Rachmady ,  Harold W. Kennel ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Jack T. Kavalieros ,  Anand S. Murthy

IPC: H01L21/285 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L29/739 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78

Abstract: Group III-V semiconductor devices having asymmetric source and drain structures and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. The drain structure has a wider band gap than the source structure. A gate structure is over the channel structure.

公开(公告)号：US20210305098A1

公开(公告)日：2021-09-30

申请号：US16832500

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Ehren Mannebach ,  Nafees Kabir ,  Patrick Morrow ,  Gilbert Dewey ,  Willy Rachmady ,  Anh Phan

IPC: H01L21/822 ,  H01L27/088 ,  H01L23/528 ,  H01L29/04 ,  H01L21/768 ,  H01L29/16 ,  H01L21/311 ,  H01L23/522

Abstract: Integrated circuitry comprising stacked first and second transistor structures. One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension. A dielectric material between the upper and lower transistor structures may be anisotropically etched asymmetrically by orienting a workpiece to be non-orthogonal to a reactive ion flux. Varying an angle between the reactive ion flux and a plane of the second transistor during an etch of the dielectric material may ensure an etched opening is of sufficient bottom dimension to expose a terminal of the lower-level transistor even if not perfectly aligned with the second transistor structure.

公开(公告)号：US20210074704A1

公开(公告)日：2021-03-11

申请号：US16650155

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow ,  Rishabh Mehandru

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.

公开(公告)号：US20210036023A1

公开(公告)日：2021-02-04

申请号：US16529643

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Jack Kavalieros ,  Anand Murthy ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Cheng-Ying Huang ,  Cory Bomberger

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66

Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.

公开(公告)号：US20200335501A1

公开(公告)日：2020-10-22

申请号：US16957664

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Ravi Pillarisetty ,  Rishabh Mehandru ,  Cheng-ying Huang ,  Willy Rachmady ,  Aaron Lilak

IPC: H01L27/092 ,  H01L25/07 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/778 ,  H01L29/06 ,  H01L29/78

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

公开(公告)号：US20200328278A1

公开(公告)日：2020-10-15

申请号：US16914052

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Matthew V. Metz ,  Willy Rachmady ,  Harold W. Kennel ,  Van H. Le ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/267 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.

公开(公告)号：US10748900B2

公开(公告)日：2020-08-18

申请号：US15771080

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/088

Abstract: Embodiments of the invention include a semiconductor structure and a method of making such a structure. In one embodiment, the semiconductor structure comprises a first fin and a second fin formed over a substrate. The first fin may comprise a first semiconductor material and the second fin may comprise a second semiconductor material. In an embodiment, a first cage structure is formed adjacent to the first fin, and a second cage structure is formed adjacent to the second fin. Additionally, embodiments may include a first gate electrode formed over the first fin, where the first cage structure directly contacts the first gate electrode, and a second gate electrode formed over the second fin, where the second cage structure directly contacts the second gate electrode.

公开(公告)号：US10734488B2

公开(公告)日：2020-08-04

申请号：US15752209

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Matthew V. Metz ,  Willy Rachmady ,  Harold W. Kennel ,  Van H. Le ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/267 ,  H01L27/092 ,  H01L29/10 ,  H01L27/11 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.