公开(公告)号：US20160268124A1

公开(公告)日：2016-09-15

申请号：US14821203

申请日：2015-08-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Xinyu Liu ,  Sen Huang ,  Xinhua Wang ,  Ke Wei ,  Wenwu Wang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/02 ,  H01L23/00

CPC classification number: H01L21/02271 ,  C23C16/0245 ,  C23C16/303 ,  H01L21/02164 ,  H01L21/02315 ,  H01L21/0254 ,  H01L21/02664

Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

Abstract translation: 低接口状态器件的制造方法包括在基板上的III-氮化物层上进行远程等离子体表面处理; 通过无氧转移系统将经处理的基底转移至沉积腔; 并沉积在沉积腔中的处理过的衬底上。 沉积可以是低压化学气相沉积（LPCVD）。 通过集成低损伤远程等离子体表面工艺和LPCVD，可以显着降低表面电介质和III-氮化物材料之间的界面状态。

公开(公告)号：US09431504B2

公开(公告)日：2016-08-30

申请号：US14696616

申请日：2015-04-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Yongkui Zhang ,  Zhiguo Zhao ,  Zhiyong Lu ,  Huilong Zhu

IPC: H01L29/49 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/265

CPC classification number: H01L29/4916 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545

Abstract: A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided.

Abstract translation: 提供一种半导体器件，其具有沿着第一方向在衬底上延伸的多个鳍结构; 栅极堆叠结构，其沿着第二方向延伸并跨越所述多个Fin结构，其中所述栅极堆叠结构包括栅极导电层和栅极绝缘层，并且所述栅极导电层由掺杂的多晶半导体形成; 多个鳍结构中的沟槽区域和栅极堆叠结构下方的沟槽区域; 以及多个Fin结构上的源极/漏极区域以及沿着第一方向的栅极堆叠结构的两侧。 还提供了一种制造半导体器件的方法。

公开(公告)号：US09412657B2

公开(公告)日：2016-08-09

申请号：US14943706

申请日：2015-11-17

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827

Abstract: In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

Abstract translation: 在制造半导体的方法中，透明硅（TSV）模板晶片和生产晶片形成夹层结构，其中TSV模板晶片具有均匀分布在其中的TSV结构，用于在生产晶片之间提供电连接以形成3D互连 。 通过减薄半导体晶片获得TSV模板晶片，这有助于降低蚀刻和填充的难度。 在TSV模板晶片上提供连接部件，以方便上层和下面的生产晶圆之间的互连，这有助于降低对准难度，并提高3D设备电气连接设计的便利性。

公开(公告)号：US09406549B2

公开(公告)日：2016-08-02

申请号：US14647393

申请日：2012-12-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Jun Luo ,  Chunlong Li ,  Jian Deng ,  Chao Zhao

IPC: H01L21/321 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L21/76229 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/32115 ,  H01L21/32132 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/6681

Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.

Abstract translation: 平面化处理，该方法包括在材料层上进行第一溅射，其中材料层的面积具有相对低的负载条件，用于由第一屏蔽层屏蔽的溅射，去除第一屏蔽层，以及在第二溅射 材料层以平坦化材料层。

公开(公告)号：US09385212B2

公开(公告)日：2016-07-05

申请号：US14725666

申请日：2015-05-29

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Guilei Wang ,  Huilong Zhu

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上形成沿第一方向延伸的多个翅片; 在翅片上形成沿着第二方向延伸的虚拟栅极堆叠; 在第一方向上在虚拟栅极堆叠的相对侧上形成栅极间隔物; 在第一方向上在栅极间隔物的相对侧的翅片的顶部外延生长凸起的源极/漏极区域; 通过栅极间隔物作为掩模，通过凸起的源极/漏极区进行轻掺杂离子注入，以在第一方向上在栅极间隔物的相对侧的鳍中形成源极/漏极延伸区域; 去除虚拟栅极堆叠以形成栅极沟槽; 以及在栅极沟槽中形成栅叠层。

公开(公告)号：US20160181363A1

公开(公告)日：2016-06-23

申请号：US14905307

申请日：2013-10-22

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou Yin ,  Rui Li

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/02164 ,  H01L21/0217 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833

Abstract: Provided is a MOSFET comprising: a substrate (100); a gate stack (500) on the substrate (100); source/drain regions (305) in the substrate on both sides of the gate stack (500); an interlayer dielectric layer (400) covering the source/drain regions; and source/drain extension regions (205) under edges on both sides of the gate stack (500); wherein insulators, which are not connected each other, are formed beneath the source/drain extension regions (205) under edges on both sides of the gate stack (500). By means of the MOSFET in the present disclosure, negative effects induced by DIBL on device performance can be effectively reduced.

Abstract translation: 提供一种MOSFET，其包括：衬底（100）; 在基板（100）上的栅极堆叠（500）; 源极/漏极区（305）位于栅叠层（500）两侧的衬底中; 覆盖所述源/漏区的层间介电层（400）; 以及源极/漏极扩展区域（205），位于栅极堆叠（500）两侧的边缘下方; 其中彼此不连接的绝缘体形成在栅极堆叠（500）的两侧的边缘下方的源极/漏极延伸区域（205）的下方。 通过本发明中的MOSFET，可以有效地降低DIBL对器件性能的负面影响。

公开(公告)号：US20160172446A1

公开(公告)日：2016-06-16

申请号：US14905440

申请日：2013-10-22

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou YIN

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L21/308 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOSFET and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100), a dummy gate structure (200), a epitaxial protection layer (101) and a sacrificial spacer (205); b. covering the dummy gate structure (200) and the substrate (100) on one side thereof by a mask layer, and forming a vacancy (102) in the substrate; c. growing a semiconductor layer (300) on the semiconductor structure to fill in the vacancy (102); d. removing the epitaxial protection layer (101) and the sacrificial spacer (205), and sequentially forming source/drain extension regions, a spacer (201), source/drain regions, and an interlayer dielectric layer (500); and e. removing the dummy gate structure (200) to form a dummy gate vacancy, and forming a gate stack in the dummy gate vacancy. In the MOSFET structure of the present disclosure, negative effects of DIBL on device performance can be effectively reduced.

Abstract translation: 公开了一种MOSFET及其制造方法。 该方法包括：a。 提供衬底（100），伪栅极结构（200），外延保护层（101）和牺牲间隔物（205）; b。 通过掩模层在其一侧覆盖伪栅极结构（200）和衬底（100），并在衬底中形成空位（102）; C。 在半导体结构上生长半导体层（300）以填充空位（102）; d。 去除外延保护层（101）和牺牲间隔物（205），顺序地形成源极/漏极延伸区域，间隔物（201），源极/漏极区域和层间介电层（500）; 和e。 去除伪栅极结构（200）以形成虚拟栅极空位，以及在虚拟栅极空位中形成栅极堆叠。 在本公开的MOSFET结构中，可以有效地降低DIBL对器件性能的负面影响。

公开(公告)号：US20160163832A1

公开(公告)日：2016-06-09

申请号：US14904140

申请日：2013-10-22

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou YIN ,  Yunfei LIU

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer on the fin; d. forming a shallow trench isolation on both sides of the fin; e. forming a sacrificial gate stack and a spacer on the top surface and sidewalls of the channel region which is in the middle of the fin; f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack; h. removing the sacrificial gate stack stack to form a sacrificial gate vacancy and expose the channel region and the channel protective layer; i. covering a portion of the semiconductor structure in one end of the fin with a photoresist layer; j. removing a portion of the spacer not covered; k. removing the photoresist layer and filling a gate stack in the sacrificial gate vacancy; l. planarizing the semiconductor structure formed by the foregoing steps to expose the channel protective layer and forming a first separated gate stack and a second separated gate stack. Comparing with the prior art, control ability of independent-gate-voltage FinFET can be effectively improved and it is good for device performance.

Abstract translation: 提供了一种FinFET制造方法，包括：a。 提供衬底; b。 在基板上形成翅片; C。 在翅片上形成通道保护层; d。 在鳍的两侧形成浅沟槽隔离; e。 在鳍的中间的沟道区的顶表面和侧壁上形成牺牲栅叠层和间隔物; F。 在鳍的两端形成源/漏区; G。 在所述牺牲栅极堆叠和所述源极/漏极区域上沉积层间电介质层，以稍后平坦化以暴露所述牺牲栅极堆叠; H。 去除牺牲栅极堆叠堆叠以形成牺牲栅极空位并暴露沟道区域和沟道保护层; 一世。 用光致抗蚀剂层覆盖鳍的一端中的半导体结构的一部分; j。 去除未覆盖的间隔件的一部分; k。 去除光致抗蚀剂层并在牺牲栅极空位中填充栅极堆叠; l。 平面化由上述步骤形成的半导体结构以暴露沟道保护层并形成第一分离的栅极堆叠和第二分离栅极堆叠。 与现有技术相比，可以有效提高独立栅极电压FinFET的控制能力，对器件性能有好处。

公开(公告)号：US20160155844A1

公开(公告)日：2016-06-02

申请号：US14904711

申请日：2013-10-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou YIN ,  Keke ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7835 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78603 ,  H01L29/78696

Abstract: A method for manufacturing an asymmetric super-thin SOIMOS transistor is disclosed. The method comprises: a. providing a substrate composed of an insulating layer (200) and a semiconductor layer (300); b. forming a gate stack (304) on the substrate; c. removing semiconductor materials of the semiconductor layer (300) on a source region side to form a first vacancy (001); d. removing insulating materials of the insulating layer (200) in the source region and under channel near the source region to form a second vacancy (002); e. filling semiconductor materials into the first vacancy (001) and the second vacancy (002) to connect with the semiconductor materials above the second vacancy (002); and f. performing source/drain implantation. Compared with the prior art, the method of the disclosure can suppress the short channel effects and enhance device performance.

Abstract translation: 公开了一种用于制造不对称超薄SOIMOS晶体管的方法。 该方法包括：a。 提供由绝缘层（200）和半导体层（300）组成的基板; b。 在所述基板上形成栅叠层（304）; C。 去除源区域侧的半导体层（300）的半导体材料以形成第一空位（001）; d。 去除所述源极区域中的所述绝缘层（200）的绝缘材料，以及在所述源极区域附近的通道以形成第二空位（002）; e。 将半导体材料填充到第一空位（001）和第二空位（002）中以与第二空位（002）之上的半导体材料连接; 和f。 进行源/漏植入。 与现有技术相比，本发明的方法可以抑制短信道效应并增强设备性能。

公开(公告)号：US20160148799A1

公开(公告)日：2016-05-26

申请号：US14662963

申请日：2015-03-19

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei WANG ,  Jinbiao Liu ,  Junfeng Li

IPC: H01L21/02 ,  H01L21/265

CPC classification number: H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02312 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/265

Abstract: The present disclosure provides a method of manufacturing a semiconductor device having silicon nitride with a tensile stress, the method comprising: c1) introducing and pre-stabilizing NH3 gas and N2 gas; c2) introducing silane; c3) igniting the gases by a radio-frequency source; c4) depositing SiN; and c5) processing the SiN by using a nitrogen ion implantation. According to the present disclosure, the nitrogen content in the SiN film can be enhanced by the nitrogen ion implantation and impinging, thereby increasing the density of the film. In this way, the acid resistance of the SiN with tensile stress is enhanced, so that the SiN with tensile stress may be integrated in a dual-strained liner of a gate-last process, so as to effectively improve the properties and reliability of the device.

Abstract translation: 本公开提供一种制造具有拉伸应力的氮化硅的半导体器件的方法，所述方法包括：c1）引入和预稳定NH 3气体和N 2气体; c2）引入硅烷; c3）用射频源点燃气体; c4）沉积SiN; 和c5）通过使用氮离子注入来处理SiN。 根据本公开，通过氮离子注入和冲击，可以提高SiN膜中的氮含量，从而提高膜的密度。 以这种方式，具有拉伸应力的SiN的耐酸性得到提高，使得具有拉伸应力的SiN可以集成在最后工艺的双应变衬里中，从而有效地提高了最终工艺的性能和可靠性 设备。