公开(公告)号：US20170207157A1

公开(公告)日：2017-07-20

申请号：US15375241

申请日：2016-12-12

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO ,  Yuko YAMAMOTO

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/30 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/29195 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A method for manufacturing a semiconductor package includes: forming an insulating layer on a support plate; forming a via in the insulating layer; locating a semiconductor device on the insulating layer such that an electrode of the semiconductor device is on the via; removing the support plate; forming a seed layer on a surface of the insulating layer opposite to the semiconductor device, in the via, and on a surface of the electrode of the semiconductor device; and forming a metal layer in the via.

公开(公告)号：US20170170106A1

公开(公告)日：2017-06-15

申请号：US15366064

申请日：2016-12-01

Applicant: J-Devices Corporation

Inventor： Naoki HAYASHI

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92144 ,  H01L2224/92244

Abstract: Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.

公开(公告)号：US20170148766A1

公开(公告)日：2017-05-25

申请号：US15422981

申请日：2017-02-02

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Hiroaki MATSUBARA ,  Shotaro SAKUMOTO

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3142 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29191 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/43

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

公开(公告)号：US20170005044A1

公开(公告)日：2017-01-05

申请号：US15198785

申请日：2016-06-30

Applicant: J-DEVICES CORPORATION

Inventor： Kiminori ISHIDO ,  Michiaki TAMAKAWA ,  Toshihiro IWASAKI

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/19105

Abstract: The present invention is to provide a semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.

Abstract translation: 本发明提供一种半导体器件，其中绝缘材料层不包含玻璃布或无纺布等增强纤维，并且能够使金属薄膜布线层小型化，金属通孔的直径减小， 层间厚度减小。 半导体器件包括绝缘材料层，其包括用不含增强纤维的绝缘材料密封的一个或多个半导体元件，多个金属薄膜布线层，将金属薄膜布线层电连接在一起的金属通孔和电极 半导体元件和金属薄膜布线层在一起，以及布置在绝缘材料层的一个主表面上的翘曲调节层，以抵消绝缘材料层的翘曲，以减少半导体器件的翘曲。

公开(公告)号：US09412685B2

公开(公告)日：2016-08-09

申请号：US14099288

申请日：2013-12-06

Applicant: J-DEVICES CORPORATION

Inventor： Yoshiyuki Tomonaga ,  Mitsuru Ooida ,  Katsumi Watanabe ,  Hidenari Sato

IPC: H01L21/44 ,  H01L23/495 ,  H01L23/31 ,  H01L23/433 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically connected to the plurality of external terminals on a front surface, a semiconductor chip mounted on the front surface of the substrate, a surface of the chip including a plurality of bonding pads, a plurality of bonding wires connecting between the plurality of bonding pads or between the plurality of bonding terminals and the plurality of bonding wires respectively, a first sealing layer sealing the front surface of the substrate, the plurality of bonding wires and the semiconductor chip, and a second sealing layer comprised of the same material as the first sealing, the second sealing layer being formed above the first sealing layer.

Abstract translation: 一种半导体器件，具有在后表面上具有多个外部端子的基板和与前表面上的多个外部端子电连接的多个接合端子，安装在基板的前表面上的半导体芯片， 所述芯片包括多个接合焊盘，多个接合线，分别连接在所述多个接合焊盘之间或者在所述多个接合端子和所述多个接合线之间，密封所述衬底的前表面的第一密封层， 的接合线和半导体芯片，以及由与第一密封件相同的材料构成的第二密封层，第二密封层形成在第一密封层的上方。

公开(公告)号：US20160172580A1

公开(公告)日：2016-06-16

申请号：US14963970

申请日：2015-12-09

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki MATSUBARA ,  Toshihiro IWASAKI ,  Tomoshige CHIKAI ,  Kiminori ISHIDO ,  Shinji WATANABE ,  Michiaki TAMAKAWA

IPC: H01L43/02 ,  H01L43/08

CPC classification number: H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall with a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Abstract translation: 一种非易失性磁存储元件的磁屏蔽封装，包括：软磁材料支撑板12; 形成在支撑板上的第一绝缘材料层13; 固定在第一绝缘材料层上的非易失性磁存储元件11; 封装存储元件及其周边的第二绝缘材料层14; 在第二绝缘材料层中，布线层15，软磁性层15b或25以及连接存储元件的电路表面的电极和布线层的导电部分16; 以及磁屏蔽部17，所述磁屏蔽部17包含与所述存储元件的侧面间隔一定距离地形成为壁的软磁性材料，以便部分或全部地包围所述存储元件侧表面，所述磁屏蔽部磁性地连接到所述软磁 层。

公开(公告)号：US09362200B2

公开(公告)日：2016-06-07

申请号：US14744946

申请日：2015-06-19

Applicant: J-DEVICES CORPORATION

Inventor： Hirokazu Honda ,  Shinji Watanabe ,  Toshihiro Iwasaki ,  Kiminori Ishido ,  Koichiro Niwa ,  Takeshi Miyakoshi ,  Sumikazu Hosoyamada ,  Yoshikazu Kumagaya ,  Tomoshige Chikai ,  Shingo Nakamura ,  Shotaro Sakumoto ,  Hiroaki Matsubara

IPC: H01L23/12 ,  H01L21/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/40 ,  H01L23/13

CPC classification number: H01L23/3675 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/4006 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2224/83

Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.

Abstract translation: 一种半导体封装，包括布置有在后侧到达半导体器件的第一孔的支撑衬底，半导体器件通过粘合剂粘合到支撑衬底的表面，覆盖半导体器件的绝缘层和用于连接 半导体器件和通过绝缘层的外部端子。 粘合剂可以形成第一孔的一部分。 此外，可以在第一孔中布置散热部，并且可以在第一孔中填充金属材料。

公开(公告)号：US20150371915A1

公开(公告)日：2015-12-24

申请号：US14739829

申请日：2015-06-15

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO ,  Yasuyuki TAKEHARA

IPC: H01L23/31 ,  H01L23/544 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0224 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.

Abstract translation: 半导体封装包括支撑衬底; 设置在所述支撑基板的主表面上的应力松弛层; 位于应力松弛层上的半导体器件; 覆盖半导体器件的封装材料，封装材料由与应力松弛层不同的绝缘材料形成; 穿过封装材料并电连接到半导体器件的线; 以及与该线路电连接的外部端子。 在支撑基板具有A的弹性模量的情况下，应力松弛层的弹性模量为B，封装材料在相同的温度条件下具有C的弹性模量，A> C> B或C> A的关系 > B。

公开(公告)号：US20140104953A1

公开(公告)日：2014-04-17

申请号：US14052864

申请日：2013-10-14

Applicant: J-DEVICES CORPORATION

Inventor： Satoru ITAKURA ,  Akio Katsumata ,  Akihiro Umeki ,  Yasushi Shiraishi ,  Junichiro Abe

IPC: G11C16/30 ,  H01L21/66

CPC classification number: G11C16/30 ,  G06F3/00 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1069 ,  G11C11/4096 ,  H01L22/10 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19105

Abstract: A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Abstract translation: 半导体存储装置100包括其底表面上具有BGA端子的控制器封装110; 每个包括多个半导体存储元件并安装在控制器封装上的一个或多个存储器封装120。 所述控制器封装包括在其底表面上具有所述BGA端子的底部基板; 电源IC，安装在底部基板上，用于供给多个电源; 以及控制器，其安装在所述底部基板上并且可由所述电源IC提供的所述多个电源操作。 控制器通过BGA端子提供与外部系统的接口，并控制来自半导体存储元件的读取操作和对半导体存储元件的写入操作。

公开(公告)号：US11322431B2

公开(公告)日：2022-05-03

申请号：US16745920

申请日：2020-01-17

Applicant: J-Devices Corporation

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.