-
公开(公告)号：WO1993010493A1
公开(公告)日：1993-05-27
申请号：PCT/US1992009463
申请日：1992-11-12
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： MICROCHIP TECHNOLOGY INC. , YACH, Randy, L. , MITRA, Sumit
IPC: G06F11/00
CPC classification number: G06F1/24 , G06F11/221
Abstract: A microcontroller (10) is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller (10) includes a power supply (70, 85) for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller (10) is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply (70, 85) is in a predetermined range and the clock frequency supplied by the clock is stable.
Abstract translation: 微控制器（10）在操作时适于执行程序和指令，并且作为响应，适于产生控制信号以选择性地控制外部设备。 微控制器（10）包括用于在适合于其操作的预定范围内向整个装置供电的电源（70,85）和用于向微控制器提供时钟频率的时钟，其具有适于精确定时和计数的稳定性 在设备内。 微控制器（10）被选择性地复位以防止它执行用于产生控制信号的程序和指令，并且尽管开始从复位状态移除直到电源提供的电力 70,85）处于预定范围，并且由时钟提供的时钟频率是稳定的。
-
公开(公告)号：WO2022245390A1
公开(公告)日：2022-11-24
申请号：PCT/US2021/060229
申请日：2021-11-20
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： GREENE, Jonathan W. , DEREVLEAN, Marcel
IPC: H03K19/17728 , H03K19/17732
Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry‑in input CI. The carry circuit generates a sum output S and a carry‑out output CO. The carry circuit can be configured to provide S = CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S = EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S = EXOR(Y, CI) and CO = CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).
-
公开(公告)号：WO2022231683A1
公开(公告)日：2022-11-03
申请号：PCT/US2022/017323
申请日：2022-02-22
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： NORRIE, Christopher I., W.
IPC: G06F9/30
Abstract: In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.
-
公开(公告)号：WO2022132288A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/053280
申请日：2021-10-03
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： TERSTRUP, Morten
IPC: H04L49/1546 , H04L49/20 , H04L49/25 , H04L49/00
Abstract: A network switch and associated method of operation for establishing a low latency transmission path through the network which bypasses the packet queue and scheduler of the switch fabric. The network switch transmits each of a plurality of data packets to the identified destination egress port over the low latency transmission if the data packet is identified to be transmitted over the low latency transmission path from the ingress port to the destination egress port, and transmits the data packet to the destination egress port through the packet queue and scheduler if the data packet is not identified to be transmitted over the low latency transmission path from the ingress port to the destination egress ports.
-
公开(公告)号：WO2022132287A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/053279
申请日：2021-10-03
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： ZUOLO, Lorenzo , MICHELONI, Rino
Abstract: A method for performing a neural network operation includes receiving weight and bias values of a deep neural network (DNN). An array of feature values, a bias value and a set of weight values for a single layer of the DNN are coupled to a neural network engine. Multiply-and-accumulate operations are performed on the single layer at one or more multiply and accumulate circuit (MAC) to obtain a sum corresponding to each neuron in the single layer. A layer output value corresponding to each neuron in the single layer is coupled to a corresponding input of the MAC. The coupling a bias value and a set of weight values, the performing multiply-and-accumulate operations and the coupling a layer output value are repeated to generate an output-layer-sum corresponding to each output-layer neuron and an activation function is performed on each output-layer-sum to generate DNN output values.
-
Patent Agency Ranking116.发明申请
公开(公告)号：WO2022108618A1
公开(公告)日：2022-05-27
申请号：PCT/US2021/030228
申请日：2021-04-30
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： ZUOLO, Lorenzo , MICHELONI, Rino
Abstract: A method and apparatus for determining when actual wear of a flash memory device differs from a reliability state. Configuration files of a reliability-state classification neural network model are stored. The operation of a flash memory device is monitored to identify current physical characteristic values. A read of the flash memory device is performed to determine a number of errors. A neural network operation is performed using as input a set of threshold voltage shift offset values currently being used to perform reads of the flash memory device and the calculated number of errors, to identify a predicted reliability state. The identified current physical characteristic values are compared to corresponding tags associated with the predicted reliability state and a flag or other indication is stored when the comparison indicates that the identified current physical characteristic values do not correspond to the respective tags associated with the predicted reliability state.
-
公开(公告)号：WO2021216113A1
公开(公告)日：2021-10-28
申请号：PCT/US2020/056353
申请日：2020-10-19
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： GRAUMANN, Peter John Waldemar
Abstract: A system and method for data sampler drift compensation in a SerDes receiver. Off-data values are received at a drift compensation engine from a plurality of data value selectors coupled to one of a plurality of data sampler pairs of a speculative Decision Feedback Equalizer (DFE) of a SerDes receiver. A drift compensation value for each of the data samplers is generated by the drift compensation engine based upon the off-data values received from each of the plurality of data value selectors and, a sampling level of each of the data samplers of the plurality of data sampler pairs of the DFE is adjusted based upon the drift compensation value from the drift compensation engine.
-
公开(公告)号：WO2021002883A1
公开(公告)日：2021-01-07
申请号：PCT/US2019/052662
申请日：2019-09-24
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： MCCOLLUM, John L. , XUE, Fengliang
Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.
-
公开(公告)号：WO2020204981A1
公开(公告)日：2020-10-08
申请号：PCT/US2019/044861
申请日：2019-08-02
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： YAP, Matthew Kian Chin , NAKAMOTO, Alan
IPC: H03K19/177
Abstract: An integrated circuit includes a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network. A plurality of configurable logic function circuits is also disposed on the integrated circuit, each configurable logic function circuit being disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.
-
公开(公告)号：WO2017062142A1
公开(公告)日：2017-04-13
申请号：PCT/US2016/051712
申请日：2016-09-14
Applicant: MICROCHIP TECHNOLOGY INC.
Inventor： KO, Isaac , HO, Ka, Wai , CHAN, Wan, Tim
IPC: H03K17/687 , H04B1/48
CPC classification number: H03K17/693 , H03K17/6874 , H04B1/48
Abstract: An improved analog switch for use in an ultrasound elastography probe is disclosed. The improved analog switch results in less heat dissipation compared to prior art analog switches.
Abstract translation: 公开了一种用于超声弹性成像探针的改进的模拟开关。 与现有技术的模拟开关相比，改进的模拟开关导致更少的散热。
-
-
-
-
-
-
-
-
-
Search Results
425
records
(took 0.032 seconds)
