적층형칩인덕터
    111.
    发明公开
    적층형칩인덕터 失效
    芯片电感器

    公开(公告)号:KR1020000040048A

    公开(公告)日:2000-07-05

    申请号:KR1019980055593

    申请日:1998-12-17

    CPC classification number: H01F17/0013 H01F27/34

    Abstract: PURPOSE: A chip inductor is provided to reducing the manufacturing cost of the chip inductor by removing the marking of the displaying section. CONSTITUTION: A chip inductor comprises at least one first ceramic sheet(105,107,109), a plurality of second ceramic sheet(101,103), at least one third ceramic sheet(111,113,115,117), and at least one through-holes(101c,103c). A conductive pattern is formed in the first ceramic sheet(105,107,109), and the conductive pattern is electrically connected to the conductive pattern of the ceramic sheet. The second ceramic sheet(101,103) are stacked above and under the first ceramic sheet(105,107,109), and are electrically connected to the conductive pattern. The third ceramic sheets(111,113,115,117) are stacked above and under the first and second ceramic sheet(105,107,109,101,103).

    Abstract translation: 目的:提供芯片电感器,通过去除显示部分的标记来降低芯片电感器的制造成本。 构成:芯片电感器包括至少一个第一陶瓷片(105,107,109),多个第二陶瓷片(101,103),至少一个第三陶瓷片(111,113,115,117)和至少一个通孔(101c,103c)。 在第一陶瓷片(105,107,109)中形成导电图案,并且导电图案电连接到陶瓷片的导电图案。 第二陶瓷片(101,103)在第一陶瓷片(105,107,109)的上方和下方堆叠,并且与导电图案电连接。 第三陶瓷片(111,113,115,117)堆叠在第一和第二陶瓷片(105,107,109,101,103)的上方和下方。

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