公开(公告)号：MX2021000357A

公开(公告)日：2021-03-25

申请号：MX2021000357

申请日：2019-07-05

Applicant: PANASONIC IP CORP AMERICA

Inventor： LIM CHONG SOON ,  SUN HAI WEI ,  TOMA TADAMASA ,  NISHI TAKAHIRO ,  ABE KIYOFUMI ,  SHASHIDHAR SUGHOSH PAVAN ,  TEO HAN BOON ,  LI JING YA ,  LIAO RU LING

IPC: H04N19/52

Abstract: Un codificador (100) incluye circuitería (160) y memoria (162) conectada a la circuitería (160). En operación, la circuitería (160): selecciona una primera tabla que se va a usar para una división actual que se va a codificar en una imagen de un video, de entre tablas que se usan para corregir un vector de movimiento base en una dirección predeterminada que usa un valor de corrección especificado por un índice, las tablas que incluyen valores de corrección que tienen diferencias variables entre índices; escribe un parámetro que indica un primer índice que se va a seleccionar de entre índices incluidos en la primera tabla; y codifica la división actual que usa el vector de movimiento base corregido al usar un valor de corrección especificado por el primer índice.

公开(公告)号：AU2019274735A1

公开(公告)日：2020-12-10

申请号：AU2019274735

申请日：2019-05-09

Applicant: PANASONIC IP CORP AMERICA

Inventor： TOMA TADAMASA ,  NISHI TAKAHIRO ,  ABE KIYOFUMI ,  KANOH RYUICHI ,  LIM CHONG SOON ,  SHASHIDHAR SUGHOSH PAVAN ,  LIAO RU LING ,  SUN HAI WEI ,  TEO HAN BOON ,  LI JING YA

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: A coding device (100) performs division into a plurality of blocks by using a block division mode set obtained by combining one or more block division modes which define division types. The block division mode set comprises: a first block division mode in which the number of divisions and the dividing direction for dividing a first block are defined; and a second block division mode in which the number of divisions and the dividing direction for dividing a second block, which is one of blocks acquired by dividing the first block are defined. When a division in the first block mode results in three blocks, the second block is the center block among the blocks acquired by dividing the first block, and the dividing direction of the second block division mode is the same as the dividing direction of the first block division mode, then the second block division mode includes only a block division mode in which a division results in three blocks.

公开(公告)号：CA3238600A1

公开(公告)日：2019-11-28

申请号：CA3238600

申请日：2019-05-09

Applicant: PANASONIC IP CORP AMERICA

Inventor： TOMA TADAMASA ,  NISHI TAKAHIRO ,  ABE KIYOFUMI ,  KANOH RYUICHI ,  LIM CHONG SOON ,  SHASHIDHAR SUGHOSH PAVAN ,  LIAO RU LING ,  SUN HAI WEI ,  TEO HAN BOON ,  LI JING YA

Abstract: An encoder partitions into blocks using a set of block partition modes obtained by combining one or more block partition modes defining a partition type. The set of block partition modes includes a first partition mode defining the partition direction and number of partitions for partitioning a first block, and a second block partition mode defining the partition direction and number of partitions for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode includes only a block partition mode indicating that the number of partitions is three.

公开(公告)号：CA3072997A1

公开(公告)日：2019-02-28

申请号：CA3072997

申请日：2018-08-10

Applicant: PANASONIC IP CORP AMERICA

Inventor： ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA ,  KANOH RYUICHI ,  LIM CHONG SOON ,  LIAO RU LING ,  SUN HAI WEI ,  SHASHIDHAR SUGHOSH PAVAN ,  TEO HAN BOON ,  LI JING YA

IPC: H04N19/117 ,  H04N19/157 ,  H04N19/80

Abstract: An image encoder is provided, which includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, performs a boundary smoothing operation along a boundary between a first partition having a non-rectangular shape (e.g., a triangular shape) and a second partition that are split from an image block. The boundary smoothing operation includes: first-predicting first values of a set of pixels of the first partition along the boundary, using information of the first partition; second-predicting second values of the set of pixels of the first partition along the boundary, using information of the second partition; weighting the first values and the second values; and encoding the first partition using the weighted first values and the weighted second values.

公开(公告)号：AU2011241708B2

公开(公告)日：2015-09-24

申请号：AU2011241708

申请日：2011-04-11

Applicant: PANASONIC IP CORP AMERICA

Inventor： DRUGEON VIRGINIE ,  SHIBAHARA YOUJI ,  NISHI TAKAHIRO ,  SASAI HISAO ,  TANIKAWA KYOKO

IPC: H04N19/11 ,  H04N19/593

Abstract: In a spatial prediction method which can reduce the complexity of spatial prediction, a horizontal gradient (Gy) and a vertical gradient (Gx) between pixels in an adjacent block which is adjacent to a block which is the subject of prediction are acquired, and thus an edge (E) which overlaps with the block which is the subject of prediction is detected (S10); the integer incline of the detected edge is calculated (S11); and for each pixel position in the block which is the subject of prediction, a fractional pixel position (450) which has the calculated integer incline, and is the intersection point between a line (430) which passes through the pixel position (440), and the boundary of the adjacent block is determined (S12); the pixel value of the pixel position (440) for each pixel position in the block which is the subject of prediction is predicted on the basis of a pixel value which has been interpolated by the fractional pixel position (450) determined for said pixel position (S13). The boundary with the adjacent block is the closest row or column to the block which is the subject of prediction, from among the plurality of pixel rows and columns included in the adjacent block.

公开(公告)号：SG11201500612PA

公开(公告)日：2015-04-29

申请号：SG11201500612P

申请日：2013-08-07

Applicant: PANASONIC IP CORP AMERICA

Inventor： SASAI HISAO ,  NISHI TAKAHIRO ,  SHIBAHARA YOUJI ,  TANIKAWA KYOKO ,  SUGIO TOSHIYASU ,  MATSUNOBU TORU ,  TERADA KENGO

Abstract: An image decoding method of decoding, on a per-block basis, a coded image included in a bitstream, includes: performing arithmetic decoding on a current block to be decoded (S101); determining whether or not the current block is at the end of a slice(S103); determining, when it is determined that the current block is not at the end of the slice, whether or not the current block is at the end of a sub-stream which is a structural unit of the image that is different from the slice (S105); and performing arithmetic decoding on a sub-last bit and performing arithmetic decoding termination, when it is determined that the current block is at the end of the sub-stream (S106).

公开(公告)号：AU2010202485A1

公开(公告)日：2010-08-05

申请号：AU2010202485

申请日：2010-01-19

Applicant: PANASONIC IP CORP AMERICA

Inventor： LIM CHONG SOON ,  NISHI TAKAHIRO ,  SHIBAHARA YOUJI

IPC: H04M1/00 ,  H04N13/00 ,  H04N19/00 ,  H04N19/102 ,  H04N19/136 ,  H04N19/146 ,  H04N19/169 ,  H04N19/196 ,  H04N19/423 ,  H04N19/46 ,  H04N19/50 ,  H04N19/503 ,  H04N19/593 ,  H04N19/597 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/85 ,  H04N19/91

Abstract: A coding method includes: defining an access unit (S502 to S508); and coding each of the pictures included in the access unit, for each access unit (S526). The defining (S502 to S508) includes: determining a unit of coding for determining whether the pictures included in the access unit are to be uniformly coded on a per-field basis or on a per-frame basis (S502); and determining a field type for determining whether the pictures are to be uniformly coded as top fields or bottom fields (S504 to S508) when it is determined that the pictures included in the access unit are to be coded on a per-field basis. In the coding (S526), each of the pictures is coded for each access unit in a format determined in the determining of a unit of coding (S526) and in the determining of a field type (S502 to S508).

公开(公告)号：AU2023306696A2

公开(公告)日：2025-03-27

申请号：AU2023306696

申请日：2023-06-01

Applicant: PANASONIC IP CORP AMERICA

Inventor： GAO JINGYING ,  TEO HAN BOON ,  LIM CHONG SOON ,  YADAV PRAVEEN KUMAR ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA

IPC: H04N19/30 ,  H04N19/46 ,  H04N19/85

Abstract: The present invention is provided with: a circuit; and a memory connected to the circuit. In operation, the circuit decodes a first bitstream to acquire a first image, decodes a second bitstream to acquire specification information specifying a specific region in the first image and a second image including image data of the specific region, and generates a third image on the basis of the first image, the specification information, and the second image.

公开(公告)号：MX2025000827A

公开(公告)日：2025-03-07

申请号：MX2025000827

申请日：2022-02-23

Applicant: PANASONIC IP CORP AMERICA

Inventor： LI JING YA ,  LIM CHONG SOON ,  TEO HAN BOON ,  KUO CHE-WEI ,  SUN HAI WEI ,  WANG CHU TONG ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA ,  KATO YUSUKE

IPC: H04N19/52 ,  H04N19/593

Abstract: Un codificador (100) incluye circuitos y una memoria acoplada a los circuitos. Los circuitos, en funcionamiento: determinan si un tamaño de un bloque actual, que es una unidad para la que se genera una lista de candidatos a vector que incluye candidatos a vector, es menor o igual que un umbral (S3001); cuando el tamaño del bloque actual es menor o igual que el umbral (SÍ en S3001), generan la lista de candidatos a vector registrando un candidato a vector de movimiento basado en la historia (HMVP) en la lista de candidatos a vector desde una tabla HMVP sin realizar un primer proceso de poda (S3002); cuando el tamaño del bloque actual es mayor que el umbral (NO en S3001), generan la lista de candidatos a vectores realizando el primer proceso de poda y registrando el candidato a vector HMVP en la lista de candidatos a vector desde la tabla HMVP (S3003); y codifican el bloque actual usando la lista de candidatos a vector (S3004).

公开(公告)号：MX2025000823A

公开(公告)日：2025-03-07

申请号：MX2025000823

申请日：2021-08-06

Applicant: PANASONIC IP CORP AMERICA

Inventor： LIM CHONG SOON ,  SUN HAI WEI ,  TEO HAN BOON ,  LI JING YA ,  KUO CHE-WEI ,  ABE KIYOFUMI ,  TOMA TADAMASA ,  NISHI TAKAHIRO ,  KATO YUSUKE

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/119 ,  H04N19/159 ,  H04N19/176

Abstract: Se proporciona un codificador (100) que incluye: circuitería; y una memoria acoplada a la circuitería, en el cual en operación, la circuitería: genera una imagen de predicción de un bloque actual a ser procesado, por medio del uso de un primer vector de movimiento (paso S3001); y actualiza una tabla de predictores de vectores de movimiento basados en la historia (HMVP) por medio del uso de un primer candidato que tiene el primer vector de movimiento, la tabla de HMVP almacena, en un método de primera entrada-primera salida (FIFO), una pluralidad de segundos candidatos cada uno que tiene un segundo vector de movimiento usado para un bloque procesado (paso S3002), y en la actualización de la tabla de HMVP, la circuitería: determina si un tamaño del bloque actual es menor que o igual a un tamaño umbral (paso S30021); y omite la actualización de la tabla de HMVP (paso S30022) cuando se determina que el tamaño del bloque actual es menor que o igual al tamaño umbral (Si en el paso S30021).