公开(公告)号：US12127394B2

公开(公告)日：2024-10-22

申请号：US18298230

申请日：2023-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78

CPC classification number: H10B12/34 ,  H01L21/28026 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/7813 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

公开(公告)号：US12080649B2

公开(公告)日：2024-09-03

申请号：US17893349

申请日：2022-08-23

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin Shin ,  Minhyun Lee ,  Changseok Lee ,  Kyung-Eun Byun ,  Hyeonsuk Shin ,  Seokmo Hong

IPC: H01L23/532 ,  H01L23/522 ,  H10B12/00

CPC classification number: H01L23/5329 ,  H01L23/5226 ,  H10B12/30

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

公开(公告)号：US12040360B2

公开(公告)日：2024-07-16

申请号：US17735475

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Haeryong Kim ,  Hyeonjin Shin ,  Seunggeol Nam ,  Seongjun Park

IPC: H01L29/08 ,  H01L21/285 ,  H01L29/04 ,  H01L29/06 ,  H01L29/267 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L29/0847 ,  H01L21/28512 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/78 ,  H01L29/1606 ,  H01L29/165

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.

公开(公告)号：US11894469B2

公开(公告)日：2024-02-06

申请号：US16811549

申请日：2020-03-06

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Sanghyun Jo ,  Heejun Yang ,  Hyeonjin Shin ,  Shoujun Zheng

IPC: H01L29/00 ,  H01L29/88 ,  H01L29/267 ,  H01L29/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/66 ,  H01L31/032 ,  H01L29/16

CPC classification number: H01L29/882 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/267 ,  H01L29/417 ,  H01L29/66977 ,  H01L31/032

Abstract: A resonant tunneling device includes a first two-dimensional semiconductor layer including a first two-dimensional semiconductor material, a first insulating layer on the first two-dimensional semiconductor layer; and a second two-dimensional semiconductor layer on the first insulating layer and including a second two-dimensional semiconductor material of a same kind as the first two-dimensional semiconductor material.

公开(公告)号：US11887850B2

公开(公告)日：2024-01-30

申请号：US17382793

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin Shin ,  Keunwook Shin

IPC: H01L21/027 ,  H01L21/768

CPC classification number: H01L21/0274 ,  H01L21/76897

Abstract: Provided are a method of forming a carbon layer and a method of forming an interconnect structure. The method of forming a carbon layer includes providing a substrate including first and second material layers, forming a surface treatment layer on at least one of the first and second material layers, and selectively forming a carbon layer on one of the first material layer and the second material layer. The carbon layer has an sp2 bonding structure.

公开(公告)号：US11869768B2

公开(公告)日：2024-01-09

申请号：US18063909

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Changhyun Kim ,  Sang-Woo Kim ,  Kyung-Eun Byun ,  Hyeonjin Shin ,  Ahrum Sohn ,  Jaehwan Jung

IPC: H01L21/00 ,  H01L21/02

CPC classification number: H01L21/02568 ,  H01L21/0242 ,  H01L21/02376 ,  H01L21/02417 ,  H01L21/02488 ,  H01L21/02631

Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS2) substrate.

公开(公告)号：US11830952B2

公开(公告)日：2023-11-28

申请号：US17014127

申请日：2020-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Seol ,  Hyeonjin Shin ,  Minseok Yoo ,  Minhyun Lee

IPC: H01L29/786 ,  H01L29/41 ,  H01L29/417 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/16

CPC classification number: H01L29/78696 ,  H01L21/02417 ,  H01L21/02568 ,  H01L21/823412 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969

Abstract: Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

公开(公告)号：US11764156B2

公开(公告)日：2023-09-19

申请号：US17362308

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae Song ,  Seunggeol Nam ,  Yeonchoo Cho ,  Seongjun Park ,  Hyeonjin Shin ,  Jaeho Lee

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53209 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5226

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US11721781B2

公开(公告)日：2023-08-08

申请号：US17857466

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Jo ,  Jaeho Lee ,  Haeryong Kim ,  Hyeonjin Shin

IPC: H01L21/76 ,  H01L23/48 ,  H01L31/107 ,  H01L31/02 ,  H01L31/0224 ,  H01L31/0352 ,  H01S5/0687 ,  G01S7/481 ,  H01L31/028 ,  H01L31/032 ,  H01L27/146 ,  H01L31/101 ,  G01S17/931 ,  H10K39/32 ,  H01L31/0304 ,  H01L31/0296 ,  H01L31/0312 ,  H01L31/0256 ,  G05D1/02

CPC classification number: H01L31/1075 ,  G01S7/4816 ,  G01S7/4817 ,  G01S17/931 ,  H01L27/14643 ,  H01L27/14647 ,  H01L31/028 ,  H01L31/02027 ,  H01L31/022466 ,  H01L31/032 ,  H01L31/03529 ,  H01L31/035209 ,  H01L31/035281 ,  H01L31/1013 ,  H01S5/0687 ,  H10K39/32 ,  G05D1/024 ,  G05D2201/0213 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/0312 ,  H01L31/0324 ,  H01L31/035218 ,  H01L2031/0344

Abstract: A photodetector having a small form factor and having high detection efficiency with respect to both visible light and infrared rays may include a first electrode, a collector layer on the first electrode, a tunnel barrier layer on the collector layer, a graphene layer on the tunnel barrier layer, an emitter layer on the graphene layer, and a second electrode on the emitter layer. The photodetector may be included in an image sensor. An image sensor may include a substrate, an insulating layer on the substrate, and a plurality of photodetectors on the insulating layer. The photodetectors may be aligned with each other in a direction extending parallel or perpendicular to a top surface of the insulating layer. The photodetector may be included in a LiDAR system.

公开(公告)号：US20230247824A1

公开(公告)日：2023-08-03

申请号：US18298230

申请日：2023-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HUIJUNG KIM ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

IPC: H01L29/94 ,  H01L29/423 ,  H01L29/78

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/053 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/7813

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.