公开(公告)号：EP3109698A3

公开(公告)日：2017-01-18

申请号：EP16180754.0

申请日：2003-02-14

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji

IPC: G03F1/26 ,  H01L23/58 ,  H01L21/768 ,  G03F1/32

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: There is provided a semiconductor device, comprising a substrate (101) that includes an integrated circuit region (1), first and second interlayer insulation films (108, 111, 112) formed above the substrate, and a reinforcing structure comprising a main-wall part (2) and a sub-wall part (3) which are formed in the first and second interlayer insulation films, wherein the main-wall part surrounds the integrated circuit region in a periphery thereof and the sub-wall part is provided apart from the main-wall part in a corner region of the semiconductor device and is located between the integrated circuit region and the first bend section of the main-wall part. Both the main-wall part and the sub-wall part are formed by metal-filled trenches (131, 132) in the first and second interlayer insulation films.

Abstract translation: 主壁部设置为围绕集成电路部。 在主壁部的各个角部和集成电路部之间设置有“L”形的副壁部。 因此，即使由于热处理等引起的应力集中，与常规的相比，也不可能将应力分散到主壁部和副壁部，因此不易发生层之间的剥离和裂纹 艺术。 此外，即使在角部发生裂纹等，当主壁部和副壁部彼此结合时，来自外部的水分几乎不到达集成电路部。 因此，可以确保极高的耐湿性。

公开(公告)号：EP3109697A3

公开(公告)日：2017-01-18

申请号：EP16180753.2

申请日：2003-02-14

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji

IPC: G03F1/26 ,  H01L23/58 ,  H01L21/768 ,  G03F1/32

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: There is provided a semiconductor device, comprising a substrate (101) that includes an integrated circuit region (1), first and second interlayer insulation films (108, 111, 112) formed above the substrate, and a reinforcing structure comprising a main-wall part (2) and a sub-wall part (3) which are formed in the first and second interlayer insulation films, wherein the main-wall part surrounds the integrated circuit region in a periphery thereof and the sub-wall part is provided apart from the main-wall part in a corner region of the semiconductor device and is located between the integrated circuit region and the first bend section of the main-wall part. Both the main-wall part and the sub-wall part are formed by metal-filled trenches (131, 132) in the first and second interlayer insulation films.

Abstract translation: 提供了一种半导体器件，包括：衬底（101），其包括集成电路区域（1），形成在衬底上方的第一和第二层间绝缘膜（108,111,112）以及包括主壁 部分（2）和形成在所述第一层间绝缘膜和所述第二层间绝缘膜中的子壁部分（3），其中所述主壁部分在其周边围绕所述集成电路区域，并且所述子壁部分设置成与 所述主壁部分位于所述半导体器件的角落区域中并且位于所述集成电路区域和所述主壁部分的所述第一弯曲部分之间。 主壁部分和副壁部分都由第一和第二层间绝缘膜中的金属填充沟槽（131,132）形成。

公开(公告)号：EP3113216A1

公开(公告)日：2017-01-04

申请号：EP16174758.9

申请日：2016-06-16

Applicant: IMEC VZW

Inventor： Beyne, Eric

IPC: H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/02063 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/481 ,  H01L24/80 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1036 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06544 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: The present invention is related to a method for bonding and interconnecting two or more IC devices (10a,10b) arranged on substrates such as silicon wafers (1a,1b), wherein the wafers are bonded by a direct bonding technique to form a wafer assembly, and wherein the multiple IC devices are provided with metal contact structures (4a,4b). A TSV (Through Semiconductor Via) (16,30;16+16',30+30') is produced through the bonded wafer assembly, wherein the IC device or devices in upper wafer or wafers have contact structures (4a) that serve as masks for the etching of the TSV opening. A conformal isolation liner (17) is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug (18) in the TSV opening. The removal of the liner is done without applying a lithography step.

Abstract translation: 本发明涉及一种用于将布置在诸如硅晶片（1a，1b）的基板上的两个或更多个IC器件（10a，10b）接合和互连的方法，其中通过直接接合技术将晶片结合以形成晶片组件 ，并且其中所述多个IC器件设置有金属接触结构（4a，4b）。 通过键合晶片组件产生TSV（贯通半导体通孔）（16,30,16 + 16'，30 + 30'），其中上部晶片或晶片中的IC器件或器件具有接触结构（4a） 用于蚀刻TSV开口的掩模。 保持隔离衬垫（17）沉积在TSV开口中，随后从TSV开口中的底部和任何水平区域移除，同时将衬垫保持在侧壁上，随后将TSV插塞（18）沉积在TSV 开幕。 在不应用光刻步骤的情况下完成衬垫的移除。

公开(公告)号：EP2264758A3

公开(公告)日：2012-01-25

申请号：EP10177318.2

申请日：2002-12-05

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Shimizu, Noriyoshi ,  Suzuki, Takashi

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76811 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device which comprises a second insulating film (29) formed on a substantially flat surface, on which a surface of a first wiring (36) and a surface of a first insulating film (95) are continued, to cover the first wiring (36), a wiring trench (28a) formed in the second insulating film (29), connection holes (38a) formed in the second insulating film (29) to extend from the wiring trench (28a) to the first wiring (36), dummy connection holes (38b) formed in the second insulating film (29) to extend from the wiring trench (28a) to a non-forming region of the first wiring, and a second wiring (39) buried in the connection holes (38a) and the wiring trench (28a) to be connected electrically to the first wiring (36) and also buried in the dummy connection holes (38b), and formed such that a surface of the second wiring (39) and a surface of the second insulating film (29) constitute a substantially flat surface.

公开(公告)号：EP1351297A3

公开(公告)日：2006-08-30

申请号：EP03003482.1

申请日：2003-02-14

Applicant: FUJITSU LIMITED

Inventor： Watanabe, Kenichi, Fujitsu Limited ,  Kawano, Michiari, Fujitsu Limited ,  Namba, Hiroshi Fujitsu Limited ,  Sukegawa, Kazuo Fujitsu Ltd. ,  Hasegawa, Takumi, Fujitsu Limited ,  Sawada, Toyoji, Fujitsu Limited ,  Mitani, Junichi, Fujitsu Limited

IPC: H01L23/52 ,  H01L21/768 ,  G03F1/00

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in "L" shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

公开(公告)号：EP1168425A3

公开(公告)日：2006-02-08

申请号：EP01305281.6

申请日：2001-06-18

Applicant: ASM JAPAN K.K.

Inventor： Shimizu, Akira ,  Ozaki, Fumitoshi

IPC: H01L21/311 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/31116 ,  H01L21/31629 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of processing a semiconductor substrate involves etching a SiOF layer with HF or HF + H 2 0. The method can be used to form hollow structures in semiconductor substrates and thus provides a way to make interlayer insulators.

公开(公告)号：EP1280194A3

公开(公告)日：2004-08-18

申请号：EP02013435.9

申请日：2002-06-13

Applicant: Canon Sales Co., Inc. ,  Semiconductor Process Laboratory Co., Ltd.

Inventor： Shioya, Yoshimi ,  Nishimoto, Yuhko ,  Suzuki, Tomomi ,  Ikakura, Hiroshi ,  Maeda, Kazuo

IPC: H01L21/316

CPC classification number: H01L21/76834 ,  C23C16/0272 ,  C23C16/401 ,  C23C16/5096 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2221/1036

Abstract: The present invention relates to a manufacturing method of a semiconductor device in which a barrier insulating film and a main insulating film having low relative dielectric constant are sequentially formed while a wiring mainly consisting of copper film is coated. Its constitution includes the steps of: forming the barrier insulating film 35a on a substrate 21 subject to deposition, in which an electric power having a first frequency (f1) is applied to a first film forming gas containing at least silicon-containing gas and oxygen-containing gas to transform said first film forming gas into plasma and to cause reaction; and forming the main insulating film 35b having low relative dielectric constant on the barrier insulating film 35a, in which an electric power having a second frequency (f2) higher than the first frequency (f1) is applied to a second film forming gas containing at least the silicon-containing gas and the oxygen-containing gas to transform the second film forming gas into plasma and to cause reaction.

公开(公告)号：EP1351297A2

公开(公告)日：2003-10-08

申请号：EP03003482.1

申请日：2003-02-14

Applicant: FUJITSU LIMITED

Inventor： Watanabe, Kenichi, Fujitsu Limited ,  Kawano, Michiari, Fujitsu Limited ,  Namba, Hirohi, Fujitsu Limited ,  Hasegawa, Takumi, Fujitsu Limited ,  Sawada, Toyoji, Fujitsu Limited ,  Mitani, Junichi, Fujitsu Limited

IPC: H01L23/52 ,  H01L21/768 ,  G03F1/00

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in "L" shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

Abstract translation: 主壁部设置为围绕集成电路部。 在主壁部的各个角部和集成电路部之间设置有“L”形的副壁部。 因此，即使由于热处理等引起的应力集中，与常规的相比，也不可能将应力分散到主壁部和副壁部，因此不易发生层之间的剥离和裂纹 艺术。 此外，即使在角部发生裂纹等，当主壁部和副壁部彼此结合时，来自外部的水分几乎不到达集成电路部。 因此，可以确保极高的耐湿性。

公开(公告)号：EP1325516A2

公开(公告)日：2003-07-09

申请号：EP01973154.6

申请日：2001-09-18

Applicant: ACM Research, Inc.

Inventor： WANG, Hui

IPC: H01L21/44 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76835 ,  C25F3/02 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/7684 ,  H01L2221/1036

Abstract: In forming a layer of a semiconductor wafer (100), a dielectric layer is deposited on the semiconductor wafer. The dielectric layer (208) includes material having a low dielectric constant. Recessed (210) and non-recessed (211) areas are formed in the dielectric layer. A metal layer is deposited on the dielectric layer to fill the recessed areas and cover the non-recessed areas. The metal layer is then electropolished to remove the metal layer covering the non-recessed areas while maintaining the metal layer in the recessed areas.

公开(公告)号：EP1120822A1

公开(公告)日：2001-08-01

申请号：EP99940607.7

申请日：1999-09-01

Applicant: TOKYO ELECTRON LIMITED

Inventor： AKAHORI, Takashi ,  INAZAWA, Kouichiro ,  SENOO, Kouji ,  HAGIWARA, Masaaki

IPC: H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3127 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76835 ,  H01L2221/1031 ,  H01L2221/1036

Abstract: A semiconductor device using, e.g., a fluorine containing carbon film, as an interlayer dielectric film is produced by a dual damascene method which is a simple technique.
After an dielectric film, e.g., an SiO 2 film 3, is deposited on a substrate 2, the SiO 2 film 3 is etched to form a via hole 31 therein, and then, a top dielectric film, e.g., a CF film 4, is deposited on the top face of the SiO 2 film 3. If the CF film is deposited by activating a thin-film deposition material having a bad embedded material, e.g., C 6 F 6 gas, as a plasma, the CF film 4 can be deposited on the top face of the SiO2 film 3 while inhibiting the CF film from being embedded into the via hole 31. Subsequently, by etching the CF film 4 to form a groove 41 therein, it is possible to easily produce a dual damascene shape wherein the groove 41 is integrated with the via hole 31.

Abstract translation: 使用例如含氟碳膜作为层间绝缘膜的半导体器件通过双镶嵌法制造，这是一种简单的技术。 在基板2上沉积例如SiO2膜3的电介质膜之后，蚀刻SiO 2膜3以在其中形成通孔31，然后沉积顶部电介质膜例如CF膜4 在SiO 2膜3的顶面上。如果通过激活作为等离子体的具有不良嵌入材料（例如C 6 F 6气体）的薄膜沉积材料来沉积CF膜，则可以将CF膜4沉积在顶表面 同时抑制CF膜被嵌入到通孔31中。随后，通过蚀刻CF膜4以在其中形成凹槽41，可以容易地产生双镶嵌形状，其中凹槽41被集成 与通孔31.