General purpose, programmable media processor
    121.
    发明公开
    General purpose, programmable media processor 失效
    通用可编程媒体处理器

    公开(公告)号:EP1876536A3

    公开(公告)日:2008-06-25

    申请号:EP07111476.3

    申请日:1996-08-16

    Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

    Abstract translation: 一种用于处理和传输媒体数据流的通用可编程媒体处理器(12)。 媒体处理器(12)包含执行单元(100),该执行单元(100)基本上维持媒体数据流中的峰值数据。 执行单元(100)包括动态可分配多精度算术单元(102),可编程开关(104)和可编程扩展数学元件(106)。 高带宽外部接口(124)以基本上峰值速率向通用寄存器文件(110)和执行单元提供媒体数据流。 存储器管理单元,以及指令和数据高速缓冲存储器/缓冲器(118,120)。 通用可编程媒体处理器(12)设置在由光纤电缆,同轴电缆和双绞线组成的网络结构中,以发送,处理和接收单个或统一的媒体数据流。

    General purpose, programmable media processor
    123.
    发明公开
    General purpose, programmable media processor 失效
    Drahtlose Vorrichtung mit einem programmierbaren Allzweckmedienprozessor

    公开(公告)号:EP1879103A2

    公开(公告)日:2008-01-16

    申请号:EP07112545.4

    申请日:1996-08-16

    Abstract: A wireless device for processing streams of media data in a wireless bi-directional communications network. The bi-directional communications network is capable of transmitting and receiving media data streams which comprise a combination of at least two of audio, video, radio, graphics, encryption, authentication, and networking information. The wireless device has at least one programmable media processor (12) for receiving, processing and transmitting the stream of media data over the bi-directional communications network. The processor executes group instructions to read a plurality of data elements of the media data stream from a register file (110), to perform, on the data elements, group operations including both group integer and group floating point operations capable of dynamically partitioning the data by each specifying one of a plurality of data element sizes, and to write concatenated results in the register file.

    Abstract translation: 一种用于在无线双向通信网络中处理媒体数据流的无线设备。 双向通信网络能够发送和接收包括音频,视频,无线电,图形,加密,认证和网络信息中的至少两个的组合的媒体数据流。 无线设备具有至少一个可编程媒体处理器(12),用于通过双向通信网络接收,处理和发送媒体数据流。 处理器执行组指令以从寄存器文件(110)读取媒体数据流的多个数据元素,以对数据元素执行包括能够动态划分数据的组整数和组浮点运算的组操作 通过每个指定多个数据元素大小中的一个,并将连接的结果写入寄存器文件。

    MASKS FOR LITHOGRAPHIC PATTERNING USING OFF-AXIS ILLUMINATION
    126.
    发明公开
    MASKS FOR LITHOGRAPHIC PATTERNING USING OFF-AXIS ILLUMINATION 失效
    PRODUCING平版印刷图案利用光板岩面罩

    公开(公告)号:EP0744044A1

    公开(公告)日:1996-11-27

    申请号:EP95909535.0

    申请日:1995-02-09

    CPC classification number: G03F1/36 G03F7/70125 G03F7/70433

    Abstract: In a lithographical tool utilizing off-axis illumination, masks to provide increased depth of focus and minimize CD differences between certain features are disclosed. A first mask for reducing proximity effects between isolated and densely packed features and increasing depth of focus (DOF) of isolated features is disclosed. The first mask comprises additional lines (214) referred to as scattering bars, disposed next to isolated edges. The bars are spaced a distance from isolated edges such that isolated and densely packed edge gradients substantially match so that proximity effects become negligible. The width of the bars is set so that a maximum DOF range for the isolated feature is achieved. A second mask, that is effective with quadrupole illumination only, is also disclosed. This mask 'boosts' intensity levels and consequently DOF ranges for smaller square contacts so that they approximate intensity levels and DOF ranges of larger elongated contacts. Increasing the intensity levels in smaller contacts reduces critical dimension differences between variably sized contact patterns when transferred to a resist layer. The second mask comprises additional openings, referred to as anti-scattering bars, disposed about the square contact openings. The amount of separation between the edge of the smaller contact and the anti-scattering bars determines the amount of increased intensity. The width of the anti-scattering bars determines the amount of increase in DOF range. Both scattering bar and anti-scattering bars are designed to have widths significantly less than the resolution of the exposure tool so that they do not produce a pattern during exposure of photoresist.

    A BURST MODE MEMORY ACCESSING SYSTEM
    127.
    发明公开
    A BURST MODE MEMORY ACCESSING SYSTEM 失效
    SHOCK操作存储器系统

    公开(公告)号:EP0701733A1

    公开(公告)日:1996-03-20

    申请号:EP94919985.0

    申请日:1994-04-28

    CPC classification number: G11C7/1039 G11C5/025

    Abstract: A large burst mode memory (10) accessing system (15) includes N discrete sub-memories (11, 12) and three main I/O ports (17, 18, 19). Data is stored in the sub-memories so that the sub-memories (11, 12) are accessed depending on their proximity to the main I/O ports (17, 18, 19). Three parallel pipelines (1, 2, 3) provide a data path to/from the main I/O ports (17, 18, 19) and the sub-memories (11, 12). The first pipeline (1) functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline (2) functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline (3) propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

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