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187 records (took 0.021 seconds)

    121.
    发明专利
    未知

    公开(公告)号：DE68923818D1

    公开(公告)日：1995-09-21

    申请号：DE68923818

    申请日：1989-04-11

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  KRAMER KEVIN GERRARD ,  DEAN MARK EDWARD ,  TEMPEST SUSAN LYNN ,  GAUDENZI GENE JOSEPH

    IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H03K19/00 ,  H03K19/0175

    Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

    123.
    发明专利
    未知

    公开(公告)号：DK169492B1

    公开(公告)日：1994-11-07

    申请号：DK189489

    申请日：1989-04-19

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F9/38 ,  G06F12/08

    Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

    124.
    发明专利
    未知

    公开(公告)号：MX170835B

    公开(公告)日：1993-09-20

    申请号：MX1616989

    申请日：1989-05-24

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F12/08 ,  H04L12/46

    Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

    125.
    发明专利
    未知

    公开(公告)号：FI914608A

    公开(公告)日：1992-04-02

    申请号：FI914608

    申请日：1991-10-01

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

    IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G11C

    Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

    126.
    发明专利
    未知

    公开(公告)号：FR2632096B1

    公开(公告)日：1991-09-20

    申请号：FR8905077

    申请日：1989-04-11

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  MILLING PHILIP ERNA

    IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362 ,  G06F13/42

    Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

    DATA PROCESSING SYSTEMS WITH DELAYED CACHE WRITE
    128.
    发明专利
    DATA PROCESSING SYSTEMS WITH DELAYED CACHE WRITE 未知

    公开(公告)号：GB2219111B

    公开(公告)日：1991-05-29

    申请号：GB8912019

    申请日：1989-05-25

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F12/08

    Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

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