公开(公告)号：US11514639B2

公开(公告)日：2022-11-29

申请号：US17209412

申请日：2021-03-23

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Michael Apodaca ,  Kai Xiao ,  Altug Koker ,  Jeffery S. Boles ,  Adam T. Lake ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  James M. Holland ,  Prasoonkumar Surti ,  Jonathan Kennedy ,  Louis Feng ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06T19/00 ,  G06T15/06 ,  G06T15/00 ,  G06F3/01 ,  H04S7/00 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

公开(公告)号：US11501484B2

公开(公告)日：2022-11-15

申请号：US17032964

申请日：2020-09-25

Applicant: INTEL CORPORATION

Inventor： Michael Apodaca ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Timothy Rowley ,  Joshua Barczak ,  Travis Schluessler

IPC: G06T15/06 ,  G06F16/901 ,  G06F7/14 ,  G06F9/38 ,  G06N3/02 ,  G06T5/00 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US11494867B2

公开(公告)日：2022-11-08

申请号：US17115555

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Michael Apodaca ,  Aditya Navale ,  Travis Schluessler ,  Vamsee Vardhan Chivukula ,  Abhishek Venkatesh ,  Subramaniam Maiyuran

IPC: G06T1/20

Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

公开(公告)号：US20220301259A1

公开(公告)日：2022-09-22

申请号：US17684686

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US11302066B2

公开(公告)日：2022-04-12

申请号：US17018610

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US11284118B2

公开(公告)日：2022-03-22

申请号：US17111677

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Scott Janus ,  Itay Kaufman ,  Archie Sharma ,  Stanley Baran ,  Michael Apodaca ,  Prasoonkumar Surti ,  Srikanth Potluri ,  Barnan Das ,  Hugues Labbe ,  Jong Dae Oh ,  Gokcen Cilingir ,  Maria Bortman ,  Tzach Ashkenazi ,  Jonathan Distler ,  Atul Divekar ,  Mayuresh M. Varerkar ,  Narayan Biswal ,  Nilesh V. Shah ,  Atsuo Kuwahara ,  Kai Xiao ,  Jason Tanner ,  Jeffrey Tripp

IPC: H04N19/90 ,  H04N21/218 ,  G06T7/557 ,  G06T19/00 ,  G06T1/20 ,  G06T7/90

Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.

公开(公告)号：US11232531B2

公开(公告)日：2022-01-25

申请号：US15690201

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Balaji Vembu ,  Peter Doyle ,  Michael Apodaca

IPC: G06T1/20 ,  G06T15/00

Abstract: Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.

公开(公告)号：US20210390762A1

公开(公告)日：2021-12-16

申请号：US17209412

申请日：2021-03-23

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Michael Apodaca ,  Kai Xiao ,  Altug Koker ,  Jeffery S. Boles ,  Adam T. Lake ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  James M. Holland ,  Prasoonkumar Surti ,  Jonathan Kennedy ,  Louis Feng ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06T15/06 ,  G06T15/00 ,  G06T19/00 ,  G06F3/01 ,  H04S7/00

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

公开(公告)号：US20210382548A1

公开(公告)日：2021-12-09

申请号：US17233649

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  James M. Holland ,  Pattabhiraman K ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Kamal Sinha ,  Ankur N. Shah ,  Deepak S. Vembar ,  Abhishek R. Appu ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F3/01 ,  G06T15/00 ,  G06T3/40 ,  G06T1/60 ,  G06F3/16 ,  G06F3/147 ,  G06T19/00 ,  G06F3/0481 ,  G06T7/80

Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

公开(公告)号：US11158111B2

公开(公告)日：2021-10-26

申请号：US16915599

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Michael Apodaca ,  Carson Brownlee ,  Thomas Raoux ,  Joshua Barczak ,  Gabor Liktor

IPC: G06T15/06 ,  G06T1/20

Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.