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121.发明授权公开(公告)号：US11703753B2
公开(公告)日：2023-07-18
申请号：US17223568
申请日：2021-04-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minhyun Lee , Hyeonjin Shin , Seongjun Jeong , Seongjun Park
Abstract: A pellicle configured to protecting a photomask from external contaminants may include a metal catalyst layer and a pellicle membrane including a 2D material on the metal catalyst layer, wherein the metal catalyst layer supports edge regions of the pellicle membrane and does not support a central region of the pellicle membrane. The metal catalyst layer may be on a substrate, such that the substrate and the metal catalyst layer collectively support the edge region of the pellicle membrane and do not support the central region of the pellicle membrane. The pellicle may be formed based on growing the 2D material on the metal catalyst layer and etching an inner region of the metal catalyst layer that supports the central region of the formed pellicle membrane.
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公开(公告)号：US11682622B2
公开(公告)日：2023-06-20
申请号：US17165246
申请日：2021-02-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Eun Byun , Keunwook Shin , Yonghoon Kim , Hyeonjin Shin , Hyunjae Song , Changseok Lee , Changhyun Kim , Yeonchoo Cho
IPC: H01L23/532 , H01L21/768 , H01L23/522
CPC classification number: H01L23/53276 , H01L21/76802 , H01L21/76846 , H01L21/76849 , H01L21/76877 , H01L23/5226
Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.
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公开(公告)号：US11626282B2
公开(公告)日：2023-04-11
申请号：US16678115
申请日：2019-11-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eunkyu Lee , Kyung-Eun Byun , Hyunjae Song , Hyeonjin Shin , Changhyun Kim , Keunwook Shin , Changseok Lee , Alum Jung
IPC: H01L21/02 , H01L29/16 , H01L29/165
Abstract: Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.
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124.发明授权公开(公告)号：US11624127B2
公开(公告)日：2023-04-11
申请号：US17082502
申请日：2020-10-28
Applicant: Samsung Electronics Co., Ltd. , UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
Inventor： Changseok Lee , Hyeonsuk Shin , Hyeonjin Shin , Seokmo Hong , Minhyun Lee , Seunggeol Nam , Kyungyeol Ma
Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.
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公开(公告)号：US11545358B2
公开(公告)日：2023-01-03
申请号：US16851675
申请日：2020-04-17
Inventor： Changhyun Kim , Sang-Woo Kim , Kyung-Eun Byun , Hyeonjin Shin , Ahrum Sohn , Jaehwan Jung
Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS2) substrate.
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Patent Agency Ranking
公开(公告)号：US11508815B2
公开(公告)日：2022-11-22
申请号：US16928508
申请日：2020-07-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minhyun Lee , Minsu Seol , Yeonchoo Cho , Hyeonjin Shin
IPC: H01L29/10 , H01L21/02 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78
Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.
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公开(公告)号：US11463023B2
公开(公告)日：2022-10-04
申请号：US17097232
申请日：2020-11-13
Applicant: Samsung Electronics Co., Ltd. , UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
Inventor： Jae-Young Kim , Kyungeun Byun , Minsu Seol , Hyeonjin Shin , Jeongmin Baik , Jinsung Chun , Byeonguk Ye
Abstract: A triboelectric generator includes first and second electrodes spaced apart from each other, a first charging object on a surface of the first electrode facing the second electrode, a second charging object provided between the first charging object and the second electrode, and a grounding unit configured to intermittently interconnect the second charging object and a charge reservoir due to motion of the second charging object. The first charging object is configured to be positively charged due to contact. The second charging object is configured to be negatively charged due to contact.
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公开(公告)号：US11374171B2
公开(公告)日：2022-06-28
申请号：US16823865
申请日：2020-03-19
Inventor： Minhyun Lee , Dovran Amanov , Renjing Xu , Houk Jang , Haeryong Kim , Hyeonjin Shin , Yeonchoo Cho , Donhee Ham
Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.
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公开(公告)号：US11281092B2
公开(公告)日：2022-03-22
申请号：US16689221
申请日：2019-11-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungwon Lee , Minsu Seol , Dongwook Lee , Hyeonjin Shin
IPC: G03F1/62
Abstract: A pellicle for extreme ultraviolet lithography and a method of manufacturing the pellicle for extreme ultraviolet lithography are provided. The pellicle for extreme ultraviolet lithography includes a pellicle layer having a specific (or, alternatively, predetermined) thickness, a frame on an edge area of the pellicle layer and supporting the pellicle layer, and a boron implantation layer located between the pellicle layer and the frame. The boron implantation layer is spaced by a specific (or, alternatively, predetermined) distance inward from an outer periphery of the pellicle layer.
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130.发明授权公开(公告)号：US11189699B2
公开(公告)日：2021-11-30
申请号：US16428006
申请日：2019-05-31
Applicant: Samsung Electronics Co., Ltd. , THE UNIVERSITY OF CHICAGO , Center for Technology Licensing at Cornell University
Inventor： Minhyun Lee , Jiwoong Park , Saien Xie , Jinseong Heo , Hyeonjin Shin
Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.
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