公开(公告)号：US07410816B2

公开(公告)日：2008-08-12

申请号：US10807887

申请日：2004-03-24

Applicant: Makarand Gore ,  James Guo

Inventor： Makarand Gore ,  James Guo

IPC: H01L21/00

CPC classification number: B41J2/16 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1632 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1645 ,  B41J2/1646 ,  B81B3/0035 ,  B81B2201/047 ,  B81B2201/052 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method is disclosed for forming a chamber in an electronic device, including the steps of preparing an outer surface on a solidified core material, the solidified core material in a depression formed in a substrate. The method further includes establishing a layer on the prepared outer surface of the solidified core material and a portion of the substrate surrounding the depression. The established layer and the substrate define a chamber.

Abstract translation: 公开了一种用于在电子设备中形成室的方法，包括以下步骤：在固化的芯材上制备外表面，固化的芯材在形成在基板中的凹陷中。 该方法还包括在所制备的固化的芯材的外表面上建立一层，以及围绕该凹陷的该基底的一部分。 建立的层和衬底限定一个室。

公开(公告)号：US20070279457A1

公开(公告)日：2007-12-06

申请号：US11447275

申请日：2006-06-06

Applicant: Peter J. Nystrom ,  Donald J. Drake ,  Peter M. Gulvin ,  Joseph A. DeGroot ,  Jun Ma ,  Nancy Y. Jia ,  Andrew W. Hays

Inventor： Peter J. Nystrom ,  Donald J. Drake ,  Peter M. Gulvin ,  Joseph A. DeGroot ,  Jun Ma ,  Nancy Y. Jia ,  Andrew W. Hays

IPC: B41J2/06

CPC classification number: B41J2/16 ,  B41J2/14 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2002/043 ,  B81B3/001 ,  B81B2201/052 ,  B81B2203/053 ,  H02N1/006

Abstract: The present application is directed to electrostatic actuators, and methods of making electrostatic actuators. In one embodiment, an electrostatic actuator of the present application comprises a first electrode and a second electrode. The second electrode is positioned in proximity to the first electrode so as to provide a gap between the first electrode and the second electrode. The first electrode is capable of being deflected toward the second electrode. A dielectric structure comprising a dielectric landing post is positioned in the gap between the first electrode and the second electrode, the dielectric structure extending over a greater surface of the gap than the landing post. The landing post protrudes out into the gap so as to limit the minimum contact spacing between the first electrode and the second electrode.

Abstract translation: 本申请涉及静电致动器以及制造静电致动器的方法。 在一个实施例中，本申请的静电致动器包括第一电极和第二电极。 第二电极位于第一电极附近，以便在第一电极和第二电极之间提供间隙。 第一电极能够朝向第二电极偏转。 包括电介质着陆柱的电介质结构位于第一电极和第二电极之间的间隙中，电介质结构在间隙的更大表面上延伸超过着陆柱。 着陆柱突出到间隙中，以限制第一电极和第二电极之间的最小接触间距。

公开(公告)号：US20070259292A1

公开(公告)日：2007-11-08

申请号：US11780234

申请日：2007-07-19

Applicant: John Krawczyk ,  James Mrvos ,  Girish Patil ,  Jason Vanderpool ,  Brian Hart ,  Christopher Money ,  Jeanne Singh ,  Karthik Vaideeswaran

Inventor： John Krawczyk ,  James Mrvos ,  Girish Patil ,  Jason Vanderpool ,  Brian Hart ,  Christopher Money ,  Jeanne Singh ,  Karthik Vaideeswaran

IPC: G03C5/00 ,  H01L21/461 ,  H01L21/302

CPC classification number: B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1645 ,  B81B2201/052 ,  B81C1/00531

Abstract: A method of etching a semiconductor substrate. The method includes the steps of applying a photoresist etch mask layer to a device surface of the substrate. A select first area of the photoresist etch mask is masked, imaged and developed. A select second area of the photoresist etch mask layer is irradiated to assist in post etch stripping of the etch mask layer from the select second area. The substrate is etched to form fluid supply slots through a thickness of the substrate. At least the select second area of the etch mask layer is removed from the substrate, whereby mask layer residue formed from the select second area of the etch mask layer is significantly reduced.

Abstract translation: 蚀刻半导体衬底的方法。 该方法包括以下步骤：将光致抗蚀剂蚀刻掩模层施加到衬底的器件表面。 光刻胶蚀刻掩模的选择第一区被掩蔽，成像和显影。 照射光致抗蚀剂蚀刻掩模层的选择的第二区域以辅助蚀刻掩模层从选择的第二区域的后蚀刻剥离。 蚀刻基板以形成通过基板的厚度的流体供给槽。 至少蚀刻掩模层的选择第二区域从衬底去除，由此从蚀刻掩模层的选择的第二区域形成的掩模层残留物显着减少。

公开(公告)号：US07271105B2

公开(公告)日：2007-09-18

申请号：US10941404

申请日：2004-09-15

Applicant: John W. Krawczyk ,  James M. Mrvos ,  Girish S. Patil ,  Jason T. Vanderpool ,  Brian C. Hart ,  Christopher J. Money ,  Jeanne M. Saldanha Singh ,  Karthik Vaideeswaran

Inventor： John W. Krawczyk ,  James M. Mrvos ,  Girish S. Patil ,  Jason T. Vanderpool ,  Brian C. Hart ,  Christopher J. Money ,  Jeanne M. Saldanha Singh ,  Karthik Vaideeswaran

IPC: H01L21/461

CPC classification number: B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1645 ,  B81B2201/052 ,  B81C1/00531

Abstract: A method of etching a semiconductor substrate. The method includes the steps of applying a photoresist etch mask layer to a device surface of the substrate. A select first area of the photoresist etch mask is masked, imaged and developed. A select second area of the photoresist etch mask layer is irradiated to assist in post etch stripping of the etch mask layer from the select second area. The substrate is etched to form fluid supply slots through a thickness of the substrate. At least the select second area of the etch mask layer is removed from the substrate, whereby mask layer residue formed from the select second area of the etch mask layer is significantly reduced.

Abstract translation: 蚀刻半导体衬底的方法。 该方法包括以下步骤：将光致抗蚀剂蚀刻掩模层施加到衬底的器件表面。 光刻胶蚀刻掩模的选择第一区被掩蔽，成像和显影。 照射光致抗蚀剂蚀刻掩模层的选择的第二区域以辅助蚀刻掩模层从选择的第二区域的后蚀刻剥离。 蚀刻基板以形成通过基板的厚度的流体供给槽。 至少蚀刻掩模层的选择第二区域从衬底去除，由此从蚀刻掩模层的选择的第二区域形成的掩模层残留物显着减少。

公开(公告)号：US06902872B2

公开(公告)日：2005-06-07

申请号：US10208163

申请日：2002-07-29

Applicant: Diane Lai ,  Samson Berhane ,  Barry C. Snyder ,  Ronald A. Hellekson ,  Hubert Vander Plas

Inventor： Diane Lai ,  Samson Berhane ,  Barry C. Snyder ,  Ronald A. Hellekson ,  Hubert Vander Plas

IPC: B41J2/16 ,  B81B7/00 ,  H01L21/768 ,  H01L23/48 ,  H05K1/11 ,  G03F7/00

CPC classification number: B41J2/16 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1634 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2202/18 ,  B81B7/0006 ,  B81B2201/052 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K1/112 ,  H05K2201/09518 ,  H01L2924/00

Abstract: A method of manufacturing a microelectronics device is provided, wherein the microelectronics device is formed on a substrate having a frontside and a backside. The method comprises forming a circuit element on the frontside of the substrate from a plurality of layers deposited on the frontside of the substrate, wherein the plurality of layers includes an intermediate electrical contact layer, and forming an interconnect structure after forming the electrical contact layer. The interconnect structure includes a contact pad formed on the backside of the substrate, and a through-substrate interconnect in electrical communication with the contact pad, wherein the through-substrate interconnect extends from the backside of the substrate to the electrical contact layer.

Abstract translation: 提供了一种制造微电子器件的方法，其中微电子器件形成在具有前侧和背侧的衬底上。 该方法包括从沉积在基板的前侧上的多个层在基板的前侧形成电路元件，其中多个层包括中间电接触层，以及在形成电接触层之后形成互连结构。 所述互连结构包括形成在所述衬底的背面上的接触焊盘以及与所述接触焊盘电连通的贯穿衬底互连，其中所述贯通衬底互连件从所述衬底的背面延伸到所述电接触层。

公开(公告)号：US06881677B1

公开(公告)日：2005-04-19

申请号：US10803009

申请日：2004-03-17

Applicant: Girish Shivaji Patil ,  Karthik Vaideeswaran

Inventor： Girish Shivaji Patil ,  Karthik Vaideeswaran

IPC: B41J2/16 ,  H01L21/302 ,  H01L21/461

CPC classification number: B81C1/00531 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B81B2201/052

Abstract: A method for forming a fluid feed via in a semiconductor substrate chip for a micro-fluid ejection head. The method includes applying a photoresist planarization and protection layer to a first surface of the chip. The photoresist planarization and protection layer is patterned and developed to define at least one fluid feed via location. A strippable layer is applied to the photoresist planarization and protection layer on the chip. The strippable layer is patterned and developed with a photomask to define the at least one fluid feed via location in the strippable layer. The chip is then dry etched to form at least one fluid feed via in the defined feed via location. Before or after etching the chip, deprotection of the strippable layer is induced so that the strippable layer can be substantially removed with a solvent without substantially affecting the photoresist planarization and protection layer.

Abstract translation: 一种用于在用于微流体喷射头的半导体衬底芯片中形成流体供给通孔的方法。 该方法包括将光致抗蚀剂平坦化和保护层应用于芯片的第一表面。 光致抗蚀剂平坦化和保护层被图案化和显影以限定至少一个通过位置的流体馈送。 可剥离层被施加到芯片上的光致抗蚀剂平坦化和保护层。 可剥离层被图案化并用光掩模显影以限定通过可剥离层中的位置的至少一个流体进料。 然后将芯片干蚀刻以在定义的进料通过位置形成至少一个流体进料通孔。 在蚀刻芯片之前或之后，诱导可剥离层的脱保护，使得可剥离层可以基本上用溶剂除去而基本上不影响光致抗蚀剂平坦化和保护层。

公开(公告)号：US20040104454A1

公开(公告)日：2004-06-03

申请号：US10605585

申请日：2003-10-10

Applicant: ROHM CO., LTD.

Inventor： Masaki Takaoka ,  Noriyuki Shimoji

IPC: H01L029/40

CPC classification number: B81B3/007 ,  B81B2201/052 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C2201/014 ,  B81C2201/019 ,  H01L23/481 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor device is disclosed which can be miniaturized and in which structures on a semiconductor substrate therein are difficult to delaminate, as well as a method of producing the same. The semiconductor device includes a semiconductor substrate main unit, and a thin portion that is thinner than the main unit and formed such that a recessed portion is formed in the semiconductor substrate and has at least one through hole formed therein. The thin portion is formed such that the etching rate of the thin portion is slower than the etching rate of the main unit. The thin portion provides a bridging structure between both sides of the recessed portion, and can mechanically and structurally strengthen the semiconductor device with respect to forces applied from the side surfaces of the main unit of the semiconductor substrate. Thus, structures such as wires, films, and semiconductor elements formed on the main unit and/or the thin portion of the semiconductor substrate or via the through holes will be difficult to detach from the semiconductor device.

Abstract translation: 公开了可以小型化并且其中的半导体衬底上的结构难以分层的半导体器件及其制造方法。 半导体器件包括半导体衬底主单元和比主单元薄的薄部分，并且形成为在半导体衬底中形成凹部并且在其中形成有至少一个通孔。 薄部形成为使得薄部的蚀刻速度比主体的蚀刻速度慢。 薄壁部分在凹部的两侧之间提供桥接结构，并且可相对于从半导体衬底的主单元的侧表面施加的力来机械地和结构地加强半导体器件。 因此，形成在半导体基板的主单元和/或薄壁部分上或通过通孔的诸如导线，膜和半导体元件的结构将难以从半导体器件分离。

公开(公告)号：US4455192A

公开(公告)日：1984-06-19

申请号：US365923

申请日：1982-04-05

Applicant: Masayoshi Tamai

Inventor： Masayoshi Tamai

IPC: B41J2/135 ,  B41J2/16 ,  B81B1/00 ,  H01L21/308

CPC classification number: B41J2/1629 ,  B41J2/162 ,  B81C1/00087 ,  B81B2201/052

Abstract: A method for the formation of a multi-nozzle ink jet is herein disclosed. In this method a single crystal silicon plate is masked and impurities are diffused upon its surface, creating regions of echant resistance. A second single crystal silicon plate is then grown onto the first, and is masked and etched. Due to the unisotropic etching properties of single crystal silicon plates, a groove is formed in the second plate, and a plurality of nozzles is formed in the first plate. This process yields a multi-nozzle ink jet of greater overall strength and utility, while eliminating the waste due to etching run common in the manufacture of conventional ink jets.

Abstract translation: 本文公开了形成多喷嘴喷墨的方法。 在这种方法中，单晶硅板被掩蔽并且杂质在其表面上扩散，产生耐磨性的区域。 然后将第二单晶硅板生长到第一单晶硅板上，并被掩模和蚀刻。 由于单晶硅板的各向异性蚀刻性能，在第二板上形成槽，在第一板上形成多个喷嘴。 该方法产生了更大的总体强度和效用的多喷嘴喷墨，同时消除了在常规喷墨制造中普遍存在的蚀刻浪费的浪费。

公开(公告)号：US20240083741A1

公开(公告)日：2024-03-14

申请号：US18460885

申请日：2023-09-05

Applicant: ROHM CO., LTD.

Inventor： Daisuke NISHINOHARA ,  Hideaki HASHIMOTO ,  Toma FUJITA

IPC: B81B3/00

CPC classification number: B81B3/0051 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2201/042 ,  B81B2201/052 ,  B81B2203/0118 ,  B81B2203/0346

Abstract: The present disclosure provides a MEMS device having a movable portion. The MEMS device includes: a substrate; a recess, disposed in the substrate; the movable portion, hollowly supported in the recess; and a bump stop, hollowly supported in the recess and configured to restrict a movement of the movable portion by contacting the movable portion. The bump stop includes: a protruding portion, configured to contact the movable portion; and a shock absorbing portion, disposed between the protruding portion and the substrate and configured to absorb at least a part of an impact force applied to the protruding portion by elastic deformation.

公开(公告)号：US20180117910A1

公开(公告)日：2018-05-03

申请号：US15800904

申请日：2017-11-01

Applicant: ROHM Co., LTD.

Inventor： Nobufumi MATSUO

IPC: B41J2/14 ,  B81C1/00 ,  B81B1/00 ,  B41J2/16

CPC classification number: B41J2/1433 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/162 ,  B41J2/1623 ,  B41J2/1626 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1635 ,  B41J2/1642 ,  B41J2002/14491 ,  B81B1/004 ,  B81B2201/032 ,  B81B2201/052 ,  B81C1/00087 ,  B81C3/001 ,  B81C2203/032

Abstract: There is provided a nozzle substrate including a nozzle hole penetrating in a thickness direction. The nozzle substrate includes a main substrate including a first surface and a second surface, an oxidation film formed on the second surface of the main substrate, and a water repellent film formed on a surface at an opposite side to the main substrate side of the oxidation film. The nozzle hole includes a first through hole penetrating the main substrate in a thickness direction, a second through hole penetrating the oxidation film and being connected to the first through hole, and a third through hole penetrating the water repellent film and being connected to the second through hole. An inner circumference surface of the second through hole and an inner circumference surface of the third through hole are approximately flush.