公开(公告)号：WO1995020191A1

公开(公告)日：1995-07-27

申请号：PCT/US1995000650

申请日：1995-01-20

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  KREIN, William, Todd ,  FLAIG, Charles, M. ,  KELLY, James, D.

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: To optimize sytem bus utilization in a computer system, a bus coordinator is included in the computer system to coordinate the transfer of information signals on the bus. Each time a source node wishes to transfer information to a destination node, the source node sends a request to the coordinator along with the identification of the destination node. Upon receiving this request, the coordinator determines whether the destination node has capacity to receive information signals. If the destination node has capacity, then the coordinator grants control of the system bus to the source node to allow the source node to send information signals to the destination node via the system bus. Otherwise, the source node is denied control of the system bus until the destination node has capacity to receive information signals. By granting control of the system bus to a source node only when the destination node has capacity to receive information signals, the coordinator ensures that no system bus time is wasted on unsuccessful information transfers. Thus, bus utilization is optimized.

Abstract translation: 为了优化计算机系统中的系统总线利用率，计算机系统中包括总线协调器，以协调总线上信息信号的传输。 每当源节点希望将信息传送到目的地节点时，源节点与目的地节点的标识一起向协调器发送请求。 在接收到该请求之后，协调器确定目的地节点是否具有接收信息信号的能力。 如果目标节点具有容量，则协调器将系统总线的控制权授予源节点，以允许源节点通过系统总线向目的地节点发送信息信号。 否则，源节点被拒绝对系统总线的控制，直到目的节点具有接收信息信号的能力。 只有当目的地节点具有接收信息信号的能力时，通过将系统总线的控制权授予源节点，协调器才能确保不会在不成功的信息传输上浪费系统总线时间。 因此，优化了总线利用率。

公开(公告)号：WO1995020189A1

公开(公告)日：1995-07-27

申请号：PCT/US1995000801

申请日：1995-01-19

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  OHMAYE, Enio ,  JAMES, Arthur

IPC: G06F09/44

CPC classification number: G06F8/34 ,  G06F17/5009 ,  Y10S345/949

Abstract: A system and method for creating and executing interactive interpersonal computer simulations comprises an authoring editor. The authoring editor presents an authoring user interface with a comic book metaphor form for the creation of simulations. The authoring editor also provides constructs that represent chapter objects, cell objects, character objects, message objects, and thought objects to create a simulation. The authoring editor interprets the constructs and their arrangement and creates an executable simulation stored in an active simulation memory. The system also includes an engine that reads the active simulation memory, recognizes the data objects, and executes subroutines corresponding to the data objects. The engine outputs the results of the execution of the objects to the user through a simulation user interface.

Abstract translation: 用于创建和执行交互式人际计算机模拟的系统和方法包括创作编辑器。 创作编辑提供了一个创作用户界面，用于创建模拟的漫画书隐喻表单。 创作编辑器还提供了代表章节对象，单元格对象，字符对象，消息对象和思维对象的构造，以创建模拟。 创作编辑者解释构造及其布置，并创建存储在活动模拟存储器中的可执行模拟。 该系统还包括读取活动模拟存储器，识别数据对象并执行与数据对象相对应的子程序的引擎。 引擎通过模拟用户界面将对象的执行结果输出给用户。

公开(公告)号：WO1995019087A2

公开(公告)日：1995-07-13

申请号：PCT/US1995000444

申请日：1995-01-11

Applicant: APPLE COMPUTER, INC. ,  LYNCH, John ,  NICHOLS, James, B.

Inventor： APPLE COMPUTER, INC.

IPC: H04M11/06

CPC classification number: H04L29/06 ,  H04M11/06

Abstract: A low-cost yet high-performance, moderate bandwidth (up to 2 Mbps) global telecommunications interface to new and existing computers allows high-performance, low-cost telecommunications platforms to support global fax, data, voice, and other data streams in an intuitive way. The telecommunications interface provides a very low-cost solution to international connectivity for a broad class of existing computers while providing high-performance wide-area data transfer. Convenient and reliable global communications over the phone line may thus be achieved. From a rudimentary viewpoint, the telecommunications interface provides for an elegant, economical implementation of a fax/data modem. The telecommunications interface provides both a time-division multiplexed interface mode for constant bit rate communications and a packetized interface mode for variable bit rate communications. Multiple streams of digital and/or analog-derived data may be handled simultaneously. DMA and non-DMA interface mode are provided in order to achieve compatibility with a broad range of existing and new computers.

Abstract translation: 新的和现有计算机的低成本但高性能，适中带宽（高达2 Mbps）的全球电信接口允许高性能，低成本的电信平台支持全球传真，数据，语音和其他数据流 直观的方式。 电信接口为广泛的现有计算机提供了一种非常低成本的国际连接解决方​​案，同时提供高性能的广域数据传输。 因此可以实现通过电话线路的方便和可靠的全球通信。 从初步的观点来看，电信接口提供了传真/数据调制解调器的优雅，经济实现。 电信接口提供用于恒定比特率通信的时分复用接口模式和用于可变比特率通信的分组化接口模式。 可以同时处理多个数字和/或模拟派生数据流。 提供DMA和非DMA接口模式，以实现与广泛的现有和新计算机的兼容性。

公开(公告)号：WO1995009504A2

公开(公告)日：1995-04-06

申请号：PCT/US1994010441

申请日：1994-09-16

Applicant: APPLE COMPUTER, INC. ,  RIDDLE, Guy, Gregory

Inventor： APPLE COMPUTER, INC.

IPC: H04L29/06

CPC classification number: H04L29/06

Abstract: A real-time data stream is transmitted in data packets from a data source in accordance with a predetermined protocol over a shared network. Data packets of said real-time data stream are received at a data destination connected to the local area network. The data destination then reconstitutes the real-time data stream using information included in the data packets in accordance with the predetermined protocol. More particularly, a plurality of data frames are transmitted from the data source, each including at least one data packet. Each data packet includes a sequence number S identifying the data packet as the Sth data packet transmitted in the data stream and a frame number N identifying the data packet as belonging to an Nth frame transmitted in the data stream. Data packets that are the first data packets in respective frames to which they belong and data packets that are the last data packets in respective frames to which they belong include flags identifying them as such. At least some of the data packets are received at the data destination and, using sequence numbers, frame numbers, and the flags in the data packets, complete data frames received at the data destination are identified. Data frames that are timely received, as judged in relation to received data packets belonging to other frames, are forwarded to a higher-level process. Packets not belonging to complete data frames timely received are discarded. In this manner, the isochronous nature of the real-time data stream is maintained.

Abstract translation: 根据预定协议通过共享网络从数据源在数据分组中传输实时数据流。 在连接到局域网的数据目的地处接收所述实时数据流的数据分组。 然后，数据目的地使用根据预定协议包括在数据分组中的信息来重构实时数据流。 更具体地，从数据源发送多个数据帧，每个数据帧包括至少一个数据分组。 每个数据分组包括标识数据分组的序列号S，作为在数据流中发送的第S个数据分组，以及标识数据分组属于数据流中传输的第N个帧的帧号N. 作为它们所属的各个帧中的第一数据分组的数据分组和作为它们所属的各个帧中的最后数据分组的数据分组包括标识它们的标志。 至少一些数据分组在数据目的地被接收，并且使用序列号，帧号和数据分组中的标志，识别在数据目的地处接收到的完整数据帧。 根据与属于其他帧的接收数据分组判断的及时接收的数据帧被转发到更高级别的进程。 不属于完整数据帧的数据包被及时收到被丢弃。 以这种方式，保持实时数据流的同步性质。

公开(公告)号：WO1995009416A1

公开(公告)日：1995-04-06

申请号：PCT/US1994011011

申请日：1994-09-28

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  CHOW, Yen-Lu ,  DESOUZA, Peter, V. ,  FINEBERG, Adam, B. ,  HON, Hsiao-Wuen

IPC: G10L03/00

CPC classification number: G10L15/07 ,  G06K9/00154 ,  G10L15/063 ,  G10L15/144 ,  G10L2015/0635

Abstract: A pattern recognition system which continuously adapts reference patterns to more effectively recognize input data from a given source. The input data is converted to a set or series of observed vectors and is compared to a set of Markov Models. The closest matching Model is determined and is recognized as being the input data. Reference vectors which are associated with the selected Model are compared to the observed vectors and updated ("adapted") to better represent or match the observed vectors. This updating method retains the value of these observed vectors in a set of accumulation vectors in order to base future adaptations on a broader data set. When updating, the system also may factor in the values corresponding to neighboring reference vectors that are acoustically similar if the data set from the single reference vector is insufficient for an accurate calculation. Every reference vector is updated after every input; thus, reference vectors neighboring an updated reference vector may also be updated. The updated reference vectors are then stored by the computer system for use in recognizing subsequent inputs.

Abstract translation: 一种模式识别系统，其连续地适应参考模式以更有效地识别来自给定源的输入数据。 将输入数据转换为一组或一系列观测向量，并将其与一组马尔科夫模型进行比较。 确定最接近的匹配模型，并将其识别为输入数据。 将与所选模型相关联的参考向量与观察到的向量进行比较并更新（“适应”）以更好地表示或匹配观察到的向量。 这种更新方法将这些观测向量的值保留在一组累积向量中，以便将未来的适应基础放在更广泛的数据集上。 当更新时，如果来自单个参考矢量的数据集不足以进行准确的计算，则系统还可以考虑与相邻参考矢量相对应的值，该参考矢量在声学上类似。 每个参考矢量在每次输入后更新; 因此，也可以更新与更新的参考矢量相邻的参考向量。 然后更新的参考矢量由计算机系统存储以用于识别后续输入。

公开(公告)号：WO1995009394A1

公开(公告)日：1995-04-06

申请号：PCT/US1994010785

申请日：1994-09-23

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  BAXTER, Michael, A.

IPC: G06F09/38

CPC classification number: G06F9/3012 ,  G06F9/3836 ,  G06F9/3885

Abstract: A minimal instruction set computer architecture (hyperscalar computer architecture) comprises a central memory, an instruction buffer, a control unit, an I/O control unit, a plurality of functional units, a plurality of register files, and a data router. In the hyperscalar computer architecture, the central memory transfers a plurality of instructions to the instruction buffer. The control unit receives multiple instructions from the instruction buffer, and automatically determines and issues the largest subset of instructions from those received that can be simultaneously issued to the plurality of functional units. Each functional unit receives data from and returns computational results to a corresponding register file. The data router serves to transfer data between each register file and any other register file, the central memory, the control unit, or the I/O control unit. The present invention also includes a multiple instruction issue method for issuing instructions to the hyperscalar computer architecture. The multiple instruction issue method comprises the steps of: determining a set of first source register files used by a plurality of instructions; determining a set of second source register files used by the plurality of instructions; determining a set of destination register files used by the plurality of instructions; determining a largest subset of instructions within the plurality of instructions that can be executed without a register file conflict; and issuing in parallel each instruction within the largest subset to the plurality of functional units.

Abstract translation: 最小指令集计算机体系结构（超标量计算机架构）包括中央存储器，指令缓冲器，控制单元，I / O控制单元，多个功能单元，多个寄存器文件和数据路由器。 在超标量计算机架构中，中央存储器将多条指令传送到指令缓冲器。 控制单元从指令缓冲器接收多个指令，并且自动地确定并发出可以同时发出到多个功能单元的那些接收到的指令的最大子集。 每个功能单元从相应的寄存器文件接收数据并将计算结果返回给相应的寄存器文件。 数据路由器用于在每个寄存器文件和任何其他寄存器文件，中央存储器，控制单元或I / O控制单元之间传送数据。 本发明还包括用于向超标量计算机体系结构发出指令的多指令发行方法。 多指令发布方法包括以下步骤：确定由多个指令使用的一组第一源寄存器文件; 确定由所述多个指令使用的一组第二源寄存器文件; 确定由所述多个指令使用的一组目的地寄存器文件; 确定可以在没有寄存器文件冲突的情况下执行的多个指令内的最大指令子集; 以及将所述最大子集内的每个指令并行发布到所述多个功能单元。

公开(公告)号：WO1995008800A1

公开(公告)日：1995-03-30

申请号：PCT/US1994010038

申请日：1994-09-08

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  FITCH, Jonathan

IPC: G06F09/318

CPC classification number: G06F9/3017

Abstract: An apparatus for emulation routine control transfer creates a jump host instruction (JHI) containing the address of a next emulation routine during the execution of a current emulation routine and outputs the JHI at the end of current emulation routine for transfer of host processor control. The apparatus preferably comprises: an emulated program counter (EPC), a summing means, a state machine, a pointer storage means, an opcode storage means, and a jump instruction circuit. The state machine is preferably coupled to control the loading of the EPC, the loading of the opcode storage means, the summing means, the pointer storage means and the operation of the jump instruction circuit. The pointer storage means is preferably coupled between the data bus and the jump instruction circuit. The state machine preferably issues commands on the control bus and directly to the summing means and the jump instruction circuit to prefetch the next emulation routine, create a jump instruction to the beginning of the next emulation routine and assert the jump instruction on the bus at the appropriate time to transfer directly from one emulation routine to the next using the single host jump instruction. The jump host instruction is placed upon the host processor's instruction bus after execution of the final instruction within a current emulation routine. Thus, the execution of the next emulation routine begins immediately after the execution of the jump host instruction, and significant amounts of processing time associated with the dispatch loop are eliminated.

Abstract translation: 用于仿真例程控制传输的装置在执行当前仿真程序期间产生包含下一个仿真程序的地址的跳转主机指令（JHI），并在当前仿真程序结束时输出JHI以传送主处理器控制。 该装置优选地包括：仿真程序计数器（EPC），求和装置，状态机，指针存储装置，操作码存储装置和跳转指令电路。 状态机优选地被耦合以控制EPC的加载，操作码存储装置的加载，求和装置，指针存储装置和跳转指令电路的操作。 指针存储装置优选地耦合在数据总线和跳转指令电路之间。 状态机优选地在控制总线上发出命令，并且直接向求和装置和跳转指令电路预取下一个仿真程序，创建到下一个仿真程序开始的跳转指令，并在该总线上断言跳转指令 使用单个主机跳转指令的适当时间直接从一个仿真程序传输到下一个仿真程序。 在当前仿真程序中执行最终指令之后，跳转主机指令被置于主机处理器的指令总线上。 因此，下一个仿真程序的执行在执行跳转主机指令之后立即开始，并且消除与调度循环相关联的大量处理时间。

公开(公告)号：WO1995006291A1

公开(公告)日：1995-03-02

申请号：PCT/US1994009573

申请日：1994-08-26

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  LOOP, Charles

IPC: G06F17/20

CPC classification number: G06T17/20

Abstract: A system and method for modeling smooth free-form shapes using B-splines over irregular meshes in a simple and efficient manner, generating aesthetically pleasing shapes is disclosed. This method provides a low degree parametric polynomial representation. As a result, techniques for surface-surface or ray-surface intersection is faster and more robust than possible with existing techniques. In accordance with the present invention, an input mesh M is initially simplified by isolating irregularities and constraining geometry. First, the input mesh M is subjected to general refinement, whereby a new mesh M is constructed, which in turn is subjected to constrained refinement, whereby another new mesh M is constructed. After the general and constrained refinement steps, the mesh M is broken up into a set of "quad-nets" corresponding to each of its vertices. Finally, these quad nets are used as local geometry, over which, 4 cubic Bézier triangles are constructed.

Abstract translation: 公开了一种用简单而有效的方式使用B样条对不规则网格进行平滑自由形状建模的系统和方法，从而产生美观的形状。 该方法提供了低度参数多项式表示。 因此，与现有技术相比，表面或光线表面交叉的技术更快，更可靠。 根据本发明，最初通过隔离凹凸和约束几何来简化输入网格M 0。 首先，对输入网格M 0进行一般的细化处理，由此构造新的网格M 1，其进而受到限制的细化，由此构造另一个新的网格M 2。 在一般和约束的细化步骤之后，网格M 2被分解成对应于其每个顶点的一组“四网”。 最后，这些四边形网络被用作局部几何体，在其上构造了4个立方体贝塞尔三角形。

公开(公告)号：WO1995004331A1

公开(公告)日：1995-02-09

申请号：PCT/US1994008467

申请日：1994-07-26

Applicant: APPLE COMPUTER, INC. ,  CHEN, Shenchang, Eric ,  WILLIAMS, Lance

Inventor： APPLE COMPUTER, INC.

IPC: G06T15/10

CPC classification number: G06T15/205 ,  G06T2210/44

Abstract: Three-dimensional scenes are portrayed from different viewpoints by morphing two-dimensional images. Various key views of a scene are stored, along with offset maps that identify the correspondence of pixels in adjacent stored images. When an intermediate view of the scene is to be presented, one ore more stored views are interpolated through a morphing technique. Since the key views and their offset data are pre-stored, the morphing and presentation of new views can be carried out at interactive rates. By providing the ability to quickly compute many closely spaced views, the disclosed morphing technique also facilitates the rapid computation of soft shadows and motion blur in images.

Abstract translation: 通过变形二维图像，从不同的角度描绘三维场景。 存储场景的各种关键视图以及标识相邻存储图像中像素的对应关系的偏移图。 当要呈现场景的中间视图时，通过变形技术对一个存储的视图进行插值。 由于主要观点及其偏移数据已被预先存储，新视图的变形和呈现可以以交互的速度进行。 通过提供快速计算许多紧密间隔视图的能力，所公开的变形技术还有助于快速计算图像中的软阴影和运动模糊。

公开(公告)号：WO1995002862A1

公开(公告)日：1995-01-26

申请号：PCT/US1994006868

申请日：1994-06-17

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  BURKE, Glenn, S. ,  ZACHARIAS, Gail

IPC: G06F09/355

CPC classification number: G06F9/449

Abstract: The invention is a new object construct (40) that allows a functional object in a dynamic language to be efficiently used as both a directly-invoked function and as a method in a generic function. To accomplish this use, the new object construct comprises four distinct but related contiguous storage regions designated as a header (41), a meth-info field (42), a fn-prolog field (43), and the method body (44). When called as a component of a generic function, one entry point is at the method body or at the method-information field. When called directly, another entry point exists at the function prolog field.

Abstract translation: 本发明是一种新的对象结构（40），其允许动态语言中的功能对象被有效地用作直接调用的函数和作为通用函数中的方法。 为了完成这个使用，新的对象结构包括被指定为标题（41），技术信息字段（42），fn-序列字段（43）和方法体（44）的四个不同但有关的连续存储区域， 。 当被称为通用函数的组件时，一个入口点位于方法体或方法信息字段。 当直接调用时，函数prolog字段中存在另一个入口点。