公开(公告)号：US20040250165A1

公开(公告)日：2004-12-09

申请号：US10649682

申请日：2003-08-28

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Tetsushi Tanizaki

IPC: H02H003/05

CPC classification number: G11C29/48 ,  G11C2029/3202

Abstract: A boundary scan cell in a semiconductor memory device (memory core) is provided corresponding to each terminal for performing a boundary scan test. A test controller and a read/write control circuit cause the boundary scan cell to latch input write data in a late write operation, until a next write cycle of the write cycle at which the write data was input from the terminal.

Abstract translation: 半导体存储器件（存储器核心）中的边界扫描单元对应于每个用于执行边界扫描测试的端子被提供。 测试控制器和读/写控制电路使得边界扫描单元在迟写操作中锁存输入写入数据，直到写入数据从终端输入的写周期的下一个写周期为止。

公开(公告)号：US20040250143A1

公开(公告)日：2004-12-09

申请号：US10786588

申请日：2004-02-26

Applicant: Renesas Technology Corp.

Inventor： Michiaki Kuroiwa

IPC: G06F001/26

CPC classification number: G06F1/26 ,  G06F1/08 ,  G06F1/305

Abstract: In a flash memory write mode, a microcomputer operation mode setting circuit sets a mode setting signal at one level. At this stage, a voltage drop caused by an LPF formed of a resistor, an inductor, and a capacitor can be suppressed at a low level. In a mode other than the flash memory write mode, the microcomputer operation mode setting circuit sets the mode setting signal at another level. At this stage, high frequency noise can be removed by the LPF formed of the resistor, the inductor, and the capacitor.

Abstract translation: 在闪存写入模式中，微机操作模式设置电路将模式设置信号设置在一个级别。 在这个阶段，由电阻器，电感器和电容器形成的LPF引起的电压降可以被抑制在低水平。 在闪存写入模式以外的模式中，微型计算机操作模式设置电路将模式设置信号设置在另一个级别。 在这个阶段，由电阻器，电感器和电容器形成的LPF可以去除高频噪声。

公开(公告)号：US20040246805A1

公开(公告)日：2004-12-09

申请号：US10689344

申请日：2003-10-21

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Koji Nii

IPC: G11C005/00

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C11/413

Abstract: Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.

Abstract translation: 电平控制信号都设置为H电平，电源线的电位都设置为低于电源电位。 以这种方式，可以显着地减少存储单元阵列的等待和写入操作期间的栅极泄漏电流。 电平控制信号分别设置为L电平和H电平，并且仅一个电源线的电位被设置为低于电源电位。 以这种方式，可以减少在存储单元阵列的读取操作期间的功耗。

公开(公告)号：US20040243877A1

公开(公告)日：2004-12-02

申请号：US10827288

申请日：2004-04-20

Applicant: Renesas Technology Corp.

Inventor： Kazuo Sakamoto ,  Naozumi Morino ,  Ikuo Kudo

IPC: G06F001/04

CPC classification number: G06F5/06 ,  G06F1/10

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract translation: 即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。 在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路， 与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号 存储卡。

公开(公告)号：US20040241944A1

公开(公告)日：2004-12-02

申请号：US10878247

申请日：2004-06-29

Applicant: Renesas Technology Corp.

Inventor： Kozo Katayama ,  Yoshiaki Kamigaki ,  Shinichi Minami

IPC: G11C011/34

CPC classification number: H01L27/115 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L29/7923

Abstract: Disclosed herein is a nonvolatile memory device having a plurality of nonvolatile memory cells. In the nonvolatile memory cell, a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side so that each of the memory cells stores information therein. The memory gate electrode and the switch gate electrodes extend in the same direction. Thus, even if a high voltage is applied to the memory gate electrode of each write-intended memory cell which uses the memory gate electrode and switch gate electrodes in common, and write and write blocking voltages are applied through the first and second signal electrodes, each memory cell intended for write non-selection can avoid the application of a high electric field thereto owing to the switch gate electrodes held in a cut-off state.

Abstract translation: 这里公开了具有多个非易失性存储单元的非易失性存储器件。 在非易失性存储单元中，在栅极绝缘膜和介于其间的栅极氮化物膜的第一半导体区域上形成存储栅电极。 第一和第二开关栅电极以及用作源/漏电极的第一和第二信号电极形成在存储栅电极的两侧。 从源极将电子注入到栅极氮化物膜中，使得每个存储单元在其中存储信息。 存储栅电极和开关栅电极沿相同方向延伸。 因此，即使对共用存储栅电极和开关栅电极的每个写入型存储单元的存储栅电极施加高电压，并且通过第一和第二信号电极施加写和写分断电压， 用于写入不选择的每个存储单元可以避免由于开关栅电极保持在截止状态而向其施加高电场。

公开(公告)号：US20040238875A1

公开(公告)日：2004-12-02

申请号：US10883807

申请日：2004-07-06

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Hiroaki Nakai

IPC: H01L029/76

CPC classification number: G05F1/465 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A threshold compensating circuit generates a bias potential VBIAS, that is, a threshold voltage of a MOS transistor offset by a given value. A gate-source voltage having compensation for variation in threshold voltage is thus applied to a transistor. By using a differential amplifier having this transistor as a current source, a voltage down-converter less susceptible to variation in threshold voltage caused by process variation and temperature can be implemented.

Abstract translation: 阈值补偿电路产生偏置电位VBIAS，即偏置给定值的MOS晶体管的阈值电压。 因此，对晶体管施加具有对阈值电压的变化的补偿的栅源电压。 通过使用具有该晶体管作为电流源的差分放大器，可以实现对由过程变化和温度引起的阈值电压变化较小的电压下变频器。

公开(公告)号：US20040233927A1

公开(公告)日：2004-11-25

申请号：US10679460

申请日：2003-10-07

Applicant: Renesas Technology Corp.

Inventor： Takashi Hirosawa

IPC: H04L012/413

CPC classification number: H04L12/4015 ,  H04L12/413

Abstract: In a network in which a plurality of terminals share one communication channel, signal collision is avoided and a predetermined signal is transmitted with a higher priority level. Priority levels are defined so that they are common to all the packets to be sent by nodes (including terminals and relating devices) on a network. Respective slots that regulate timing for sending out packets are assigned to the respective priority levels. Each slot is determined with reference to a time at which an ongoing packet transmission on the communication channel has finished. The priority levels are allocated in such a manner that packets having higher priority levels (packets to be sent out with higher priority) are allocated to slots having earlier timing.

Abstract translation: 在多个终端共享一个通信信道的网络中，避免信号冲突，并以更高的优先级发送预定的信号。 定义优先级，使得它们对于由网络上的节点（包括终端和相关设备）发送的所有分组是共同的。 调整发送数据包的定时的各个时隙被分配给相应的优先级。 参考通信信道上正在进行的分组传输已经完成的时间来确定每个时隙。 分配优先级，使得具有较高优先级的分组（具有较高优先级的要发送的分组）被分配给具有较早定时的时隙。

公开(公告)号：US20040218452A1

公开(公告)日：2004-11-04

申请号：US10851159

申请日：2004-05-24

Applicant: RENESAS TECHNOLOGY CORP

Inventor： Takaharu Tsuji

IPC: G11C007/00

CPC classification number: G11C11/15

Abstract: Each of N memory blocks of first to Nth stages includes a plurality of first and second driver units. The plurality of first and second driver units are respectively provided corresponding to one end and another end of a plurality of digit lines included in each memory block. Each of the first driver units in memory blocks before a selected memory block connects a corresponding digit line to a first voltage according to a voltage level on a digit line of the same row in a memory block of a previous stage. A second driver unit in the selected memory block connects a corresponding digit line to a second voltage in order to supply a data write current. In other words, digit lines in the memory blocks before the selected memory block are not used as current lines but as signal lines.

公开(公告)号：US20040203257A1

公开(公告)日：2004-10-14

申请号：US10697277

申请日：2003-10-31

Applicant: Renesas Technology Corp.

Inventor： Takeshi Yoshida ,  Tohru Koyama ,  Yoji Mashiko

IPC: H01L021/26 ,  H01L021/00 ,  G02B003/00 ,  H01L031/0232 ,  C03C015/00

CPC classification number: H01L21/268 ,  G02B3/00

Abstract: A processing technique of a semiconductor substrate which can improve a capability of a solid immersion lens in case of processing the semiconductor substrate and forming the solid immersion lens on its surface is provided. A focused ion beam (5) is irradiated on a semiconductor substrate (1), and a salient part (2) acting as a solid immersion lens is formed on its main surface (3a). At this time, a cutting amount of the semiconductor substrate (1) by the focused ion beam (5) is adjusted by making the irradiation time of the focused ion beam (5) to the semiconductor substrate (1) change. According to this, a surface of the salient part (2) has a curved surface of high precision, and a capability of the salient part (2) as the solid immersion lens is improved.

Abstract translation: 提供了半导体衬底的处理技术，其可以在处理半导体衬底并在其表面上形成固体浸没透镜的情况下提高固体浸没透镜的能力。 聚焦离子束（5）照射在半导体衬底（1）上，并且在其主表面（3a）上形成用作固体浸没透镜的突出部分（2）。 此时，通过使聚焦离子束（5）对半导体基板（1）的照射时间发生变化来调整通过聚焦离子束（5）的切割量的半导体基板（1）。 据此，突出部（2）的表面具有高精度的曲面，提高了作为固体浸没透镜的突出部（2）的能力。

公开(公告)号：US20040202253A1

公开(公告)日：2004-10-14

申请号：US10731026

申请日：2003-12-10

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Toshiaki Hanibuchi

IPC: H04B003/00

CPC classification number: H04L25/14 ,  H04L7/0008

Abstract: An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a receiver. The transmitter includes a data transmitting unit that transmits a data signal through the data signal transmission lines, depending on a transmit clock; and control transmitting units that transmit control signals through the control transmission lines, depending on the transmit clock. The receiver includes a receive clock generator that generates a read clock from the control signals; and a data receiving unit that receives the data signal through the data signal transmission line, depending on the read clock.

Abstract translation: 异步数据发送装置包括数据信号传输线; 分别具有最小延迟和最大延迟的两个控制传输线; 发射机 和接收器。 发射机包括数据发送单元，其根据发送时钟通过数据信号传输线路发送数据信号; 以及根据发送时钟通过控制传输线路发送控制信号的控制发送单元。 接收机包括从控制信号产生读时钟的接收时钟发生器; 以及数据接收单元，其根据读取的时钟通过数据信号传输线接收数据信号。