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公开(公告)号:AU2013276800B2
公开(公告)日:2016-08-18
申请号:AU2013276800
申请日:2013-05-03
Applicant: IBM
Inventor: GREINER DAN , JACOBI CHRISTIAN , SLEGEL TIMOTHY
Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.
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公开(公告)号:AU2012382778B2
公开(公告)日:2016-08-18
申请号:AU2012382778
申请日:2012-11-26
Applicant: IBM
Inventor: GREINER DAN , JACOBI CHRISTIAN , SLEGEL TIMOTHY
Abstract: A transaction begin instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.
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公开(公告)号:AU2015238632A1
公开(公告)日:2016-08-04
申请号:AU2015238632
申请日:2015-03-19
Applicant: IBM
Inventor: GREINER DAN , FARRELL MARK , OSISEK DAMIAN LEO , SCHMIDT DONALD WILLIAM , BUSABA FADI YUSUF , KUBALA JEFFREY PAUL , BRADBURY JONATHAN DAVID , HELLER LISA CRANTON , SLEGEL TIMOTHY , GAINEY JR CHARLES , JACOBI CHRISTIAN
Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.
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公开(公告)号:AU2013276133B2
公开(公告)日:2016-06-30
申请号:AU2013276133
申请日:2013-06-12
Applicant: IBM
Inventor: GREINER DAN , JACOBI CHRISTIAN , SLEGEL TIMOTHY
IPC: G06F9/46
Abstract: A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block.
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公开(公告)号:AU2012382780B2
公开(公告)日:2016-06-23
申请号:AU2012382780
申请日:2012-11-26
Applicant: IBM
Inventor: GREINER DAN , SLEGEL TIMOTHY , JACOBI CHRISTIAN , RELSON PETER JEREMY , PHILLEY RANDALL WILLIAM
IPC: G06F12/00
Abstract: An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.
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公开(公告)号:GB2526040B
公开(公告)日:2016-03-02
申请号:GB201516536
申请日:2014-02-11
Applicant: IBM
Inventor: GREINER DAN , NERZ BERND , VISEGRADY TAMAS
IPC: G06F7/58
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公开(公告)号:CY1112694T1
公开(公告)日:2016-02-10
申请号:CY121100375
申请日:2012-04-20
Applicant: IBM
Inventor: GREINER DAN , GAINEY JR CHARLES , HELLER LISA , OSISEK DAMIAN , SLEGEL TIMOTHY , SITTMANN III GUSTAV
Abstract: Αποκαλύπτεταιμίαλειτουργίαδιαχείρισηςπλαισίουορισμούκλειδιούκαιεκκαθάρισηςπουορίζεταιγιαμίααρχιτεκτονικήμηχανήςενόςσυστήματοςυπολογιστή. Σεμίαμορφήπραγματοποίησης, λαμβάνεταιμίαεντολήμηχανής, ηοποίαταυτοποιείένανπρώτοκαιένανδεύτερογενικόκαταχωρητή. Απότονπρώτογενικόκαταχωρητή, λαμβάνεταιέναπεδίομεγέθουςπλαισίου, τοοποίοδείχνειανέναπλαίσιοαποθήκευσηςείναιένααπόέναμικρόμπλοκή έναμεγάλομπλοκδεδομένων. Απότονδεύτερογενικόκαταχωρητήλαμβάνεταιμίαδιεύθυνσητελεστέουενόςπλαισίουαποθήκευσης, μετοοποίοπρέπειναεκτελεσθείη εντολή. Αντοπλαίσιοαποθήκευσηςείναιέναμικρόμπλοκ, ηεντολήεκτελείταιμόνοστομικρόμπλοκ. Αντοδεικνυόμενοπλαίσιοαποθήκευσηςείναιέναμεγάλομπλοκδεδομένων, λαμβάνεταιαπότονδεύτερογενικόκαταχωρητήμίαδιεύθυνσητελεστέουενόςαρχικούπρώτουμπλοκδεδομένωνεντόςτουμεγάλουμπλοκδεδομένων. Ηεντολήδιαχείρισηςπλαισίουεκτελείταισεόλαταμπλοκ, ταοποίαξεκινούναπότοαρχικόπρώτομπλοκ.
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公开(公告)号:CA2940990A1
公开(公告)日:2015-10-01
申请号:CA2940990
申请日:2015-03-16
Applicant: IBM
Inventor: GREINER DAN , FARRELL MARK , OSISEK DAMIAN LEO , SCHMIDT DONALD WILLIAM , BUSABA FADI YUSUF , KUBALA JEFFREY PAUL , BRADBURY JONATHAN DAVID , HELLER LISA CRANTON , SLEGEL TIMOTHY , GAINEY CHARLES JR
IPC: G06F9/46
Abstract: A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.
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公开(公告)号:DE112013003079T5
公开(公告)日:2015-05-07
申请号:DE112013003079
申请日:2013-05-21
Applicant: IBM
Inventor: GREINER DAN , JACOBI CHRISTIAN , SLEGEL TIMOTHY , MITRAN MARCEL
Abstract: Eine Anweisung TRANSACTION BEGIN und eine Anweisung TRANSACTION END werden bereitgestellt. Die Anweisung TRANSACTION BEGIN verursacht, dass abhängig von einem Feld der Anweisung entweder eine eingeschränkte oder eine nicht eingeschränkte Transaktion eingeleitet wird. Die Anweisung TRANSACTION END beendet die Transaktion, die durch die Anweisung TRANSACTION BEGIN gestartet wurde.
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公开(公告)号:MX2014015284A
公开(公告)日:2015-04-13
申请号:MX2014015284
申请日:2012-11-22
Applicant: IBM
Inventor: GREINER DAN , SLEGEL TIMOTHY , JACOBI CHRISTIAN
IPC: G06F9/46
Abstract: Se describe una instrucción de almacenamiento no transaccional, ejecutada en modo de ejecución transaccional, que efectúa almacenamientos que no son retenidos, aún si una transacción asociada con la instrucción se aborta. Los almacenamientos incluyen información especificada por el usuario que puede facilitar la depuración de una transacción abortada.
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