公开(公告)号：DE69811571T2

公开(公告)日：2003-11-27

申请号：DE69811571

申请日：1998-05-12

Applicant: SIEMENS AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  DORTU JEAN-MARC ,  PFEFFERL KARL-PETER

IPC: G11C29/44 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, RUs are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. The VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

公开(公告)号：DE69811571D1

公开(公告)日：2003-04-03

申请号：DE69811571

申请日：1998-05-12

Applicant: SIEMENS AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  DORTU JEAN-MARC ,  PFEFFERL KARL-PETER

IPC: G11C29/44 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, RUs are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. The VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

公开(公告)号：DE69811421D1

公开(公告)日：2003-03-27

申请号：DE69811421

申请日：1998-03-23

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F11/20

Abstract: A redundancy replacement (VSRR) arrangement or method for making a memory fault-tolerant employs a plurality of variable size redundancy units (RUo - RU15), each of which encompasses a plurality of redundancy elements (RE). The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.

公开(公告)号：DE69811155D1

公开(公告)日：2003-03-13

申请号：DE69811155

申请日：1998-05-12

Applicant: SIEMENS AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  DORTU JEAN-MARC ,  PFEFFERL KARL-PETER

IPC: G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: The method of making a fault-tolerant memory device employs a variable domain redundancy replacement (VDRR) arrangement. The method includes the steps of: subdividing the memory into a plurality of primary memory arrays; defining a plurality of domains, at least one of the domains having at least a portion common to another domain to form an overlapped domain area. and wherein at least one of the domains overlaps portions of at least two of the primary arrays; allocating redundancy means to each of the domains to replace faults contained within each of the domains; and replacing at least one of the faults within one of the domains with the redundancy means coupled to the one domain, and at least one other fault of the one domain is replaced by the redundancy means coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, redundancy units are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

公开(公告)号：DE69718609D1

公开(公告)日：2003-02-27

申请号：DE69718609

申请日：1997-11-25

Applicant: IBM

Inventor： DEBROSSE JOHN ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108 ,  G06F11/20

Abstract: Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.

公开(公告)号：DE69614905D1

公开(公告)日：2001-10-11

申请号：DE69614905

申请日：1996-02-06

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  WATANABE YOHJI ,  FUJII SHUSO

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/04

Abstract: The memory comprises several word-lines and complementary bit-line pairs. A source of precharge voltage for precharges the complementary bit-line pairs. Several precharge equalisation circuits each of which comprises three field effect transistors. The one FET is connected across a corresponding complementary pair of bit-lines and the other two FET's are connected in series with a respective complementary pair of bit-lines. The gates of each of the FET's are connected to receive a precharge equalisation control signal. The precharge equalisation circuits is connected to the source of the precharge voltage. One precharge equalisation circuit precharges each of the complementary bit-line pairs. A current limiter limits the precharge current flowing into the complementary bit-line pairs to a precharge current limit value. The current limiter comprises a FET which is biased to limit current flow through the transistors to the precharge current limit value.