公开(公告)号：EP2589048A4

公开(公告)日：2017-12-20

申请号：EP11803933

申请日：2011-06-28

Applicant: HEADWAY TECH INC ,  IBM

Inventor： YANG HSU KAI ,  NAKAMURA YUTAKA ,  DEBROSSE JOHN

IPC: G11C5/08 ,  G11C7/18 ,  G11C11/16

CPC classification number: G11C11/1653 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1675

Abstract: An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

公开(公告)号：JP2000196045A

公开(公告)日：2000-07-14

申请号：JP37569999

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RADENS CARL ,  GRUENING ULRIKE ,  DEBROSSE JOHN ,  MANDELMAN JACK

IPC: H01L29/78 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain necessary insulation between a capacitor for storage and a transistor in a memory cell, using both a capacitor for storage in a vertical trench and a vertical transistor. SOLUTION: One memory cell formed in a semiconductor main body 10 includes a polycrystalline silicon packing part 22 as a capacitor for storage and one field-effect transistor. This field-effect transistor includes a source 43 formed in the sidewall of a trench, a drain 42 formed in the semiconductor main body and provided with a surface in common with the upper face of the semiconductor main body, a channel region including both vertical and horizontal parts, and a polycrystalline silicon gate at the upper part of the trench. Thus, an insulating oxide layer 28 at the top end of the polycrystalline silicon packing part, which is useful as a storage node and the polycrystalline silicon packing part which is useful as a gate conductor can be obtained in this process for manufacturing.

公开(公告)号：JPH1187641A

公开(公告)日：1999-03-30

申请号：JP18405498

申请日：1998-06-30

Applicant: SIEMENS AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  DEBROSSE JOHN

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To minimize or eliminate the area required for twisting a bit line in order to reduce the size of a dynamic random access memory, wherein each cell of a memory cell array is addressed by a word line and a bit line. SOLUTION: A lower part metal layer and an upper part metal layer, together with a dielectric layer allocated between them are provided. A first bit line among a plurality of bit lines comprises a lower part metal first bit line part mounted on the lower part metal layer, and the lower part metal first bit line part is combined to first multiple memory cells. Further, the first bit line comprises an upper part metal first bit line part mounted on the upper part metal layer also, and the upper part metal first bit line part is combined to the lower part metal first bit line part by a first contact which penetrates a dielectric layer. The first contact is allocated with one of active areas 522, 530, and 560.

公开(公告)号：JPH10162599A

公开(公告)日：1998-06-19

申请号：JP32111397

申请日：1997-11-21

Applicant: IBM

Inventor： DEBROSSE JOHN ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a redundancy block architecture configuration using a column redundancy control circuit for reducing a design space effectively. SOLUTION: A column redundancy control circuit RRDN for reducing a design space effectively is constituted in parallel in a word direction and is constituted at the bottom of a redundancy block. The architecture change lays out the redundancy control block effectively by introducing split global buses 41 and 42 that are commonly used with a local column redundancy wire, a half-length one-way column redundancy word line enable signal RWLE for reducing space, and a dispersion word line enable decoder 32 that is designed to utilize the reduced space.

公开(公告)号：WO2004112048A3

公开(公告)日：2005-04-07

申请号：PCT/EP2004006019

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G06F11/10 ,  G11C7/24 ,  G11C11/406 ,  G11C29/00 ,  G11C11/15

CPC classification number: G11C7/24 ,  G06F11/106 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

Abstract translation: 本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。 根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。 此后，读出数据位和ECC校验位，并检测和校正任何错误。 然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位 并将ECC校验位存储到存储区域。

公开(公告)号：WO2005004162A3

公开(公告)日：2005-03-31

申请号：PCT/EP2004006190

申请日：2004-06-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

Inventor： DEBROSSE JOHN ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C11/16

CPC classification number: G11C11/15

Abstract: A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.

Abstract translation: 一种将信息存储在交叉点磁存储器阵列和交叉点磁存储器装置结构中的方法。 在写入操作期间磁隧道结（MTJ）上的电压降被最小化以防止损坏阵列的MTJ。 在写入操作期间，选定的MTJ，未选定的MTJ或两者上的电压降最小化，减小MTJ上的应力，降低泄漏电流，降低功耗并增加写入裕度。

公开(公告)号：DE602004009308T2

公开(公告)日：2008-05-08

申请号：DE602004009308

申请日：2004-05-26

Applicant: IBM ,  QIMONDA AG

Inventor： DEBROSSE JOHN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/12 ,  G11C8/08 ,  G11C11/16 ,  G11C11/40

公开(公告)号：DE60304209T2

公开(公告)日：2006-12-14

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

公开(公告)号：DE60304209D1

公开(公告)日：2006-05-11

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

公开(公告)号：DE602004021187D1

公开(公告)日：2009-07-02

申请号：DE602004021187

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G11C29/00 ,  G06F11/10 ,  G11C7/24 ,  G11C11/15 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.