公开(公告)号：JPH11283365A

公开(公告)日：1999-10-15

申请号：JP35791798

申请日：1998-12-16

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C7/18 ,  G11C8/14 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To constitute a hierarchical bit line architecture and a word line architecture by providing plural local bit line pairs in respective rows to be connected to memory cells and connecting them to master bit lines. SOLUTION: A bit line architecture 20 has plural local bit lines and plural master bit line pairs in respective rows Cj of a memory array. Respective contacts 29 of via holes are connected to drains or sources of FET switches 27 which are connected to the local bit lines. Switching states of the respective switches 27 are controlled by corresponding control lines 28 prolonging in a column direction. Respective control lines 28 are connected to all switches 27 provided parallel in the column direction. True master bit lines MBLj are selectively connected to true local bit lines LBLj via the switches 27it . On the other hand, the MBLj are selectively connected to complementary local bit lines LBLi via switches 27ic .

公开(公告)号：JPH11149800A

公开(公告)日：1999-06-02

申请号：JP24707698

申请日：1998-09-01

Applicant: SIEMENS AG ,  IBM

Inventor： WONG HING ,  KIRIHATA TOSHIAKI ,  KRSNIK BOZIDAR

IPC: G06F1/06 ,  G01R31/28 ,  G01R31/30 ,  G06F1/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/12 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To perform arbitrary adjustment of internal timing easily and externally by deriving the timing of an internal control signal from an internal signal in case of normal operation mode and deriving it from an external signal being fed with an internal control signal from an external terminal in case of rest mode. SOLUTION: In case of normal access mode, a WL, timer 11 times up to generate an SA Enable signal and then an SA timer 12 times up to generate a Col nable signal. When a test mode signal (TM GSAE and TM CCSLE) is activated and the timers 11, 12 are disabled, a DRAM integrated circuit is switched to test mode. If a WL Enable signal is formed, it is formed not through the timer 11 but through an external signal '/G' and an NAND gate 13. Furthermore, the Col Enable signal is formed through an external signal '/CAS' and an NAND gate 16.

公开(公告)号：JPH11162195A

公开(公告)日：1999-06-18

申请号：JP27007898

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  WONG HING ,  KRSNIK BOZIDAR

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/04 ,  G11C29/50 ,  G11C29/56 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To realize flexible supervision of a floating condition of a bit line to surely and easily detect a defective bit line, thereby increasing a yield of a module and improving reliability, by utilizing a dummy cycle capable of being controlled in a digital manner. SOLUTION: When a test mode detects cycles of a WriteCAS, a BeforeRAS, and a WCBR to become enable, a pulse signal TEST is periodically reduced to disable an equalizer EQ in a sub-array. When a RAS becomes enable, a readout operation starts. An EQ signal remains in an L condition, and a word line WL and a sense amplifier SA are activated. Accordingly, a bit line BL/BL with leakage is determined. At this time, a cycle timing is determined by a dummy cycle capable of being controlled in a digital manner. When the dummy cycle is terminated and the RAS is disabled, the WL is reset and the SA is disabled, so that the equalizer is reset.

公开(公告)号：JPH10162599A

公开(公告)日：1998-06-19

申请号：JP32111397

申请日：1997-11-21

Applicant: IBM

Inventor： DEBROSSE JOHN ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a redundancy block architecture configuration using a column redundancy control circuit for reducing a design space effectively. SOLUTION: A column redundancy control circuit RRDN for reducing a design space effectively is constituted in parallel in a word direction and is constituted at the bottom of a redundancy block. The architecture change lays out the redundancy control block effectively by introducing split global buses 41 and 42 that are commonly used with a local column redundancy wire, a half-length one-way column redundancy word line enable signal RWLE for reducing space, and a dispersion word line enable decoder 32 that is designed to utilize the reduced space.

公开(公告)号：JPH11317093A

公开(公告)日：1999-11-16

申请号：JP7746699

申请日：1999-03-23

Applicant: IBM ,  TOSHIBA CORP

Inventor： KIRIHATA TOSHIAKI ,  DEBROSSE JOHN K ,  WATANABE YOJI ,  WONG HING

IPC: G11C29/04 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide the method and the device to restore a semiconductor memory device. SOLUTION: In order to simultaneously substitute a normal true word line and normal auxiliary word line pairs Ui and Uj , a row redundancy substituting device, which consists of a redundancy true word line and redundancy auxiliary word line pairs RUk and RU2 , is provided. While conducting the restoration, which is executed as a word line selector circuit 506 using the address rearranging system controlled by a redundancy control logic 508 and an address input 510, a normal true (auxiliary) word line is substituted by a redundancy true (auxiliary) word line. In the redundancy replacing device, the consistency in a bit map is always maintained regardless of whether the memory device is operated in a normal mode or a redundancy mode.

公开(公告)号：JPH10214133A

公开(公告)日：1998-08-11

申请号：JP36071497

申请日：1997-12-26

Applicant: SIEMENS AG ,  IBM

Inventor： WONG HING ,  KIRIHATA TOSHIAKI ,  KRSNIK BOZIDAR

IPC: G06F1/06 ,  G01R31/30 ,  G06F1/08 ,  G11C7/22

Abstract: PROBLEM TO BE SOLVED: To provide an external control means for accelerating efficient circuit design relating to a test mode for controlling the timing of the internal signals of an integrated circuit by leading out internal control signals from external signals and supplying the external signals to the external pin of the integrated circuit at the time of the test mode. SOLUTION: The control circuit is provided with two operating modes, that are a normal mode and a test mode. In the normal mode, a normal signal route is used for the timing control of the internal signals 40. The normal signal route is provided with a sub circuit 5 and the sub circuit 5 is operated by the internal signals 21 and forms output signals 31. In the test mode, a test mode signal route is used for the timing control of the internal signals 40 and the test mode signal route is provided with the sub circuit 10. By the operation of the test mode signal route, the output signals 36 of the sub circuit 10 are led out from the external signals 26. The external signals 26 are supplied to the external pin of the integrated circuit.

公开(公告)号：DE69834540D1

公开(公告)日：2006-06-22

申请号：DE69834540

申请日：1998-12-18

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C7/00 ,  G11C11/401 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14 ,  G11C11/408 ,  G11C11/409 ,  G11C16/06

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F , includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

公开(公告)号：DE60006162T2

公开(公告)日：2004-07-22

申请号：DE60006162

申请日：2000-12-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HSU L ,  WORDEMAN R ,  JOACHIM HANS-OLIVER ,  WONG HING

IPC: G11C8/08 ,  G11C8/00

Abstract: A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 muA) because Vqs on the nfet is nearly at the nfet threshold. The net active power from the entire array is less than that of a conventional configuration due to the reduced voltage swing, while the number of transistors exposed to high voltage stress is reduced from 9 to 1 and the number of buffer nfets required to reduce voltage drop across an active nfet is reduced from 8 to 1.

公开(公告)号：DE69624312D1

公开(公告)日：2002-11-21

申请号：DE69624312

申请日：1996-08-12

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C29/50 ,  G11C29/00

Abstract: A bit line pair is coupled through a pair of high-resistance pass gates (164L,164R) to a sense amp (166). During sense, the high-resistance pass gates (164L,164R) act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp (166). A control circuit (185) selectively switches on and off bit line equalisation coincident with selectively passing either the equalisation voltage or set voltages to the sense amp (166) and an active sense amp load (172,174). Further, after it is set, the sense amp (166) is selectively connected to LDLs (182,184) through low-resistance column select pass gates (178,180). Therefore, the sense amp (166) quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp (166) to a second sense amplifier and off chip. After data is passed to the LDLs (182,184), the control circuit (185) enables the active sense amp load (172,174) to pull the sense amp high side to a full up level. Additionally, because the control circuit (185) uses the equalisation voltage to disable the sense amp (166), cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. The cell signal may be selected to determine both a high and a low signal margin.

公开(公告)号：DE60006162D1

公开(公告)日：2003-11-27

申请号：DE60006162

申请日：2000-12-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HSU L ,  WORDEMAN R ,  JOACHIM HANS-OLIVER ,  WONG HING

IPC: G11C8/08 ,  G11C8/00

Abstract: A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 muA) because Vqs on the nfet is nearly at the nfet threshold. The net active power from the entire array is less than that of a conventional configuration due to the reduced voltage swing, while the number of transistors exposed to high voltage stress is reduced from 9 to 1 and the number of buffer nfets required to reduce voltage drop across an active nfet is reduced from 8 to 1.