-
公开(公告)号：US20160013104A1
公开(公告)日：2016-01-14
申请号：US14455939
申请日：2014-08-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Jia-Rong Wu , Tsung-Hung Chang , Ching-Ling Lin , Yi-Hui Lee , Chih-Sen Huang , Yi-Wei Chen , Chun-Hsien Lin
IPC: H01L21/768 , H01L23/535 , H01L29/78
CPC classification number: H01L21/76897 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/53266 , H01L23/535 , H01L29/665 , H01L29/785 , H01L2924/0002 , H01L2924/00
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。
-
公开(公告)号：US09230816B1
公开(公告)日：2016-01-05
申请号：US14629502
申请日：2015-02-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Jia-Rong Wu , Chih-Sen Huang , Yi-Wei Chen , Chia Chang Hsu
IPC: H01L21/285 , H01L29/66 , H01L21/324 , H01L21/308 , H01L21/28 , H01L21/3205
CPC classification number: H01L21/28518 , H01L21/28052 , H01L21/3081 , H01L21/32053 , H01L21/324 , H01L29/41791 , H01L29/665 , H01L29/66545 , H01L29/66795 , H01L29/785
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the gate structure and the ILD layer; forming a patterned hard mask on the dielectric layer; forming an opening in the dielectric layer and the ILD layer; performing a silicide process for forming a silicide layer in the opening; removing the patterned hard mask and un-reacted metal after the silicide process; and forming a contact plug in the opening.
Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成介电层; 在介电层上形成图案化的硬掩模; 在介电层和ILD层中形成开口; 执行在开口中形成硅化物层的硅化物工艺; 在硅化物处理后去除图案化的硬掩模和未反应的金属; 并在开口中形成接触塞。
-
公开(公告)号：US20150263137A1
公开(公告)日：2015-09-17
申请号：US14726595
申请日：2015-05-31
Applicant: United Microelectronics Corp.
Inventor： Yi-Wei Chen , Chien-Chung Huang , Kok Seen Lew
IPC: H01L29/66 , H01L21/265 , H01L21/285 , H01L21/768 , H01L29/45 , H01L29/417 , H01L29/08 , H01L29/423
CPC classification number: H01L29/66795 , H01L21/26506 , H01L21/28518 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0847 , H01L29/401 , H01L29/41766 , H01L29/41791 , H01L29/4232 , H01L29/45 , H01L29/456 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/785 , H01L2924/0002 , H01L2924/00
Abstract: A method of manufacturing a semiconductor device includes forming an epitaxial layer within a source/drain region of a semiconductor substrate, forming a fluorine-containing layer on the surface of the epitaxial layer, forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer, forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure, forming a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer, forming a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole so that the fluorine-containing layer is disposed on the periphery of the metal silicide layer.
Abstract translation: 一种制造半导体器件的方法包括：在半导体衬底的源极/漏极区域内形成外延层，在外延层的表面上形成含氟层，在栅极区域之后形成金属栅极结构，步骤 形成含氟层，形成覆盖半导体衬底，外延层和金属栅极结构的层间电介质，形成穿透层间电介质的接触孔，以露出外延层的一部分，在其上形成金属硅化物层 在接触孔的底部的外延层中，使得含氟层设置在金属硅化物层的周围。
-
公开(公告)号：US20240349493A1
公开(公告)日：2024-10-17
申请号：US18754195
申请日：2024-06-26
Inventor： Yi-Wei Chen , Hsu-Yang Wang , Chun-Chieh Chiu , Shih-Fang Tzou
IPC: H10B12/00 , H01L21/768
CPC classification number: H10B12/485 , H01L21/76804 , H01L21/76805 , H01L21/76814 , H01L21/76819 , H01L21/76895 , H10B12/053 , H10B12/482
Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
-
公开(公告)号：US11877433B2
公开(公告)日：2024-01-16
申请号：US16931397
申请日：2020-07-16
Inventor： Pin-Hong Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Li-Wei Feng , Ying-Chiao Wang , Chung-Yen Feng
IPC: H01L23/48 , H10B12/00 , H01L23/532 , H01L23/522 , H01L21/285 , H01L23/528 , H01L21/768 , H01L49/02 , H01L21/02
CPC classification number: H10B12/0335 , H01L21/28568 , H01L21/7684 , H01L21/7685 , H01L21/76831 , H01L21/76876 , H01L21/76877 , H01L23/528 , H01L23/5226 , H01L23/53266 , H01L28/91 , H10B12/31 , H10B12/315 , H01L21/0217 , H01L21/0228
Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
-
Patent Agency Ranking
公开(公告)号：US10903328B2
公开(公告)日：2021-01-26
申请号：US15943717
申请日：2018-04-03
Inventor： Po-Chun Chen , Chia-Lung Chang , Yi-Wei Chen , Wei-Hsin Liu , Han-Yung Tsai
IPC: H01L29/423 , H01L21/28 , H01L27/108 , H01L21/762
Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
-
公开(公告)号：US10651040B2
公开(公告)日：2020-05-12
申请号：US15986797
申请日：2018-05-22
Inventor： Tzu-Hao Liu , Yi-Wei Chen , Tsun-Min Cheng , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Po-Chih Wu , Pin-Hong Chen , Chun-Chieh Chiu , Tzu-Chieh Chen , Chih-Chien Liu , Chih-Chieh Tsai , Ji-Min Lin
IPC: H01L21/28 , G11C11/4097 , H01L27/108
Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
-
公开(公告)号：US10600882B2
公开(公告)日：2020-03-24
申请号：US14880275
申请日：2015-10-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Chih-Sen Huang , Yi-Wei Chen , Chun-Hsien Lin
IPC: H01L21/70 , H01L29/49 , H01L29/423
Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.
-
公开(公告)号：US10529856B2
公开(公告)日：2020-01-07
申请号：US16028187
申请日：2018-07-05
Applicant: United Microelectronics Corp.
Inventor： Man-Ling Lu , Yu-Hsiang Hung , Chung-Fu Chang , Yen-Liang Wu , Wen-Jiun Shen , Chia-Jong Liu , Ssu-I Fu , Yi-Wei Chen
IPC: H01L29/78 , H01L29/66 , H01L21/308
Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.
-
公开(公告)号：US20190319031A1
公开(公告)日：2019-10-17
申请号：US15972216
申请日：2018-05-06
Inventor： Pin-Hong Chen , Yi-Wei Chen , Chun-Chieh Chiu , Chih-Chieh Tsai , Tzu-Chieh Chen , Chih-Chien Liu
IPC: H01L27/108 , H01L21/285 , H01L21/28 , H01L21/22
Abstract: The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.
-
-
-
-
-
-
-
-
-
Search Results
167
records
(took 0.033 seconds)
