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公开(公告)号：JPH1079485A
公开(公告)日：1998-03-24
申请号：JP508697
申请日：1997-01-14
Applicant: UNITED MICROELECTRONICS CORP
Inventor： CHAO FANG-CHING
IPC: H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
Abstract: PROBLEM TO BE SOLVED: To widen a charge storage area by widening the surface of a branch conductive layer connected to a trunk conductive layer connected to a drain region of a transfer transistor and by forming an overlay conductive layer on a dielectric layer formed on an exposed face of the both of the conductive layers. SOLUTION: Trunk-polysilicon layers 34a, 34b forming a tree-type storage electrode for a capacitor of a DRAM are electrically connected to drain regions 16a, 16b of a transfer transistor in the DRAM, respectively. The cross section for each of branch polysilicon layers 28a, 28b is almost an L-shape and horizontal cross sections are generally electrically in contact with the trunk-polysilicon layers 34a, 34b. Dielectric film 36a, 36b are formed on the tree-type storage electrodes 34a, 28a and the three-type storage electrode 34b, 28b, respectively. A polysilicon counter electrode 38 facing the storage electrodes 34a, 28a and 34b, 28b is formed on the dielectric films 36a, 36b.
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公开(公告)号：JPH1079477A
公开(公告)日：1998-03-24
申请号：JP9118197
申请日：1997-04-09
Applicant: UNITED MICROELECTRONICS CORP
Inventor： CHAO FANG-CHING
IPC: H01L21/8242 , H01L27/108
Abstract: PROBLEM TO BE SOLVED: To increase a charge storage area by providing a transfer transistor and a storage capacitor which are electrically connected to a source/drain region of the transfer transistor. SOLUTION: Hollow trunk-shaped polysilicon layers 46a and 46b are formed at an opening by depositing a polysilicon layer by evaporation on a substrate 10, and furthermore, the substrate 10 is etched back. The polysilicon layers 46a and 46b respectively have inner surfaces 47a and 47b in direct contact with polysilicon layers 26a and 40a, and 20b and 40b. The polysilicon layers 26a, 40a and 46a form a storage electrode 49a, and the polysilicon layers 26b, 40b and 46b form a storage electrode 49b. Dielectric layers 48a and 48b are respectively formed on the exposed surfaces of the storage electrodes 49a and 49b. next, polysilicon oppositely located electrodes 50 are formed on the surfaces of the dielectric layers 48a and 48b.
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133.发明专利
公开(公告)号：JPH1012737A
公开(公告)日：1998-01-16
申请号：JP3937697
申请日：1997-02-24
Applicant: UNITED MICROELECTRONICS CORP
Inventor： SON KISHU , KYU SEITEN , SAI MEIKO
IPC: C23C16/04 , C23C16/20 , H01L21/28 , H01L21/285 , H01L21/768
Abstract: PROBLEM TO BE SOLVED: To provide a connection body for electric connection which has no break and high reliability for a semiconductor IC device, and its formation. SOLUTION: The aluminum plug 28 is formed through a process for forming a semiconductor constituent element on a substrate 20 which has an insulating layer 24, having a contact opening 26 for exposing a conductive area 22 of the semiconductor constituent element, formed on the top surface, a process for vacuum heat annealing of the substrate 20, and a process for connecting the conductive area 22 in the contact opening 26 on the top surface of the substrate and depositing aluminum selectively not on the top surface of the insulating layer 24, but on the exposed conductive area 22 in a CVD process that uses DMEAA (dimemethyl ether amine allene) as a precursor and is carried out at substrate temperature with deposit selectivity.
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公开(公告)号：JPH09269854A
公开(公告)日：1997-10-14
申请号：JP14748296
申请日：1996-06-10
Applicant: UNITED MICROELECTRONICS CORP
Inventor： ROGAA CHIEN , NEIRU TAI , TOMII CHIEN , UESURII JIEN
Abstract: PROBLEM TO BE SOLVED: To reduce power and to adjust a device to a standard by setting a system to a power cut mode and setting it to return to a regular operation mode in response to an external trigger signal under an appropriate situation. SOLUTION: When a central processing unit 10 executes a meaningless DO loop, the system starts a special service program for saving necessary data, a notice for power-cutting the central processing unit 10 is given to a power controller 20 and the central processing unit 10 becomes a power cut state for reducing power consumption. When a new event is started, a trigger controller 30 decides it or receives the external trigger signal. A starting resetting signal 16 is transmitted to the power controller 20 is response to the trigger signal, the power controller 20 is triggered by the signal and the power of the central processing unit 10 is restored. The power of the central processing unit 10 is supplied, necessary data is restored and the internal program is executed in response to the new event.
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公开(公告)号：JPH0982436A
公开(公告)日：1997-03-28
申请号：JP23186195
申请日：1995-09-08
Applicant: UNITED MICROELECTRONICS CORP
Inventor： SHINNFUI CHIYAN
Abstract: PROBLEM TO BE SOLVED: To secure a pin socket to a circuit board for mounting an integrated circuit. SOLUTION: This socket is formed out of a base and a plurality of socket pins 15 arranged around the base for electrical connection to the part (pins) of an integrated circuit. Furthermore, each of the socket pin 15 is provided with a connection part 17 for the convenience of soldering an additional component, or generating a shortcircuit with a part of other pins 15.
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Patent Agency Ranking136.发明专利
公开(公告)号：JPH08124421A
公开(公告)日：1996-05-17
申请号：JP25563994
申请日：1994-10-20
Applicant: UNITED MICROELECTRONICS CORP
Inventor： NENGU FUSHINGU RU , NINGU YANGU , JIEI SHII DENGU , DEITSUKU RIYAO
IPC: H05K1/09 , C09J9/02 , C09J11/04 , H01B1/00 , H01B1/22 , H01B5/00 , H01B5/16 , H01R11/01 , H05K3/32
Abstract: PURPOSE: To provide an adhesive for connecting a circuit member having a conductive terminal to a substrate having a mounting surface equipped with a plurality of tracks on its side part and to provide a connecting method which can secure reliable electric connection by making a conductive terminal adhere steadfastly to a necessary position. CONSTITUTION: A conductive adhesive comprises at least 10 wt.% of compressed hollow conductive particles dispersed in a non-conductive resin. A connecting method consists of the following five steps of: (a) applying the above-mentioned adhesive to a surface of a substrate on which a circuit member is to be mounted; (b) mounting a conductive terminal of the circuit member on a pre-selected conductive passage among passages, adjusting the terminal vertically to the passage with the help of adhesive; (c) applying a magnetic field vertically to a complex consisting of a combination of a mounting surface, the adhesive, and the circuit member and collecting conductive particles between the conductive terminal and the passage; (d) applying a pressure to the circuit member under the existence of the magnetic field, so that a part of adhesive is made to be squeezed from between the conductive terminal and the passage; and (e) hardening the adhesive.
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公开(公告)号：JPH08123412A
公开(公告)日：1996-05-17
申请号：JP25859294
申请日：1994-10-24
Applicant: UNITED MICROELECTRONICS CORP
Inventor： CHIMAO FUAN
Abstract: PURPOSE: To provide an analog synthesized musical sound inverter with the simple structure at a low cost by proportioning an output value of the converting current to a current change of the product of envelope and tone, and feeding the current, which compensates the envelop generating unit with each other. CONSTITUTION: An envelope current generating unit 30 and a tone current generating unit 40 are connected to a right side of a referential current generating unit 20 in order. A direct current drift compensating unit 70 is formed by connecting a compensating current generating unit 50 and a current amplifying unit 60 in series. In this case, total current variable (Ib1+Ib2) of the compensating current generating unit 50 and the envelope current generating unit 30 is constant. Namely, when one of current variable is increased, the other current variable is reduced. The current amplifying unit 60 following to the compensating current generating unit 50 uses an intermediate value of tone. The output signal value I0 of an analog converter 10 is in proportion to the product of tone T and envelope E, and a D/A converter, which can achieve the effect by multiplying the tone signal and the envelope signal, is formed.
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公开(公告)号：JP2005252025A
公开(公告)日：2005-09-15
申请号：JP2004061127
申请日：2004-03-04
Inventor： RIN RYOKETSU , WU DE-HUNG , KO KOKUSHUN
IPC: G03F9/00 , G03F7/20 , H01L21/00 , H01L21/027
CPC classification number: G03F7/70633
Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for forming a pattern type photoresist layer capable of shortening a cycle time and a re-processing time in a pattern transfer process. SOLUTION: The forming method of the pattern type photoresist layer matched with a predetermined wafer layer is provided. The photoresist layer is formed on a substrate and exposed. An overlaid offset between the exposed part of the photoresist layer and the predetermined wafer layer is measured to determine whether the exposed part of the photoresist layer matches with the predetermined wafer layer or not. A development stage is effected in the case that the exposed part of the photoresist layer matches with the predetermined wafer layer. A device is also provided for forming the pattern type photoresist layer. This device feedbacks immediately the overlaid offset utilizing the method, whereby the cycle time and the re-processing time in the pattern transfer process are shortened. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 解决的问题：提供一种形成图案型光刻胶层的方法和装置，其能够缩短图案转印处理中的周期时间和重新处理时间。 解决方案：提供了与预定晶片层匹配的图案型光致抗蚀剂层的形成方法。 光致抗蚀剂层形成在基板上并露出。 测量光致抗蚀剂层的暴露部分和预定晶片层之间的重叠偏移，以确定光致抗蚀剂层的露出部分是否与预定晶片层匹配。 在光刻胶层的露出部分与预定的晶片层匹配的情况下，进行显影阶段。 还提供了用于形成图案型光致抗蚀剂层的装置。 该装置利用该方法立即反馈重叠的偏移，从而缩短了图案转印处理中的周期时间和重新处理时间。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2002025262A
公开(公告)日：2002-01-25
申请号：JP2000189877
申请日：2000-06-23
Applicant: UNITED MICROELECTRONICS CORP
Inventor： MEADOWS HAROLD BRETT , JOHN ALLEN FAU
IPC: G11C11/409 , G11C11/407 , H03K19/096
Abstract: PROBLEM TO BE SOLVED: To provide fast output enable path and method for an integrated circuit device which effectively minimizes gate delay in the data of a critical integrated circuit device and a clock path. SOLUTION: Several 'single shot' internal output enable clocks are generated on the basis of an external clock. Selection information is included in the parallel output enable clocks and makes it easy to multiplex some different data paths into a single output buffer. The selection information is realized at the reset part of a single shot circuit so as to be eliminated from a critical part for deciding access time.
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公开(公告)号：JP2001308307A
公开(公告)日：2001-11-02
申请号：JP2000147328
申请日：2000-05-19
Applicant: UNITED MICROELECTRONICS CORP
Inventor： CHEN MING-I , HAN ZUISHO
IPC: H01L21/76 , H01L27/06 , H01L27/146
Abstract: PROBLEM TO BE SOLVED: To provide CMOS sensor structure for forming a silicon oxide outer frame before the treatment of the injection of n+ and n-, increasing the separation distance between the n+/n- field injection regions, and at the same time reducing end junction leakage. SOLUTION: CMOS structure has a silicon oxide external frame around a sensor region. The CMOS sensor structure is equipped with a substrate, n- and n+ regions, a separation region, field injection region, and a silicon oxide external frame. The n- region is formed inside the substrate, and the n+ region is formed inside the n- region. The separation region is formed on the substrate adjacent to the end of the n- region. The field injection region is formed at the lower part of the separation region. The silicon oxide external region is formed at the upper part of the n-, separation, and n+ regions. The silicon oxide external frame can prevent surface leakage by increasing distance from the n- region to the field injection region so that end junction leakage decreases, and further performing etching.
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