公开(公告)号：JP2005311370A

公开(公告)日：2005-11-04

申请号：JP2005119732

申请日：2005-04-18

Applicant: Koninkl Philips Electronics Nv ,  St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー ,  コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィKoninklijke Philips Electronics N.V.

Inventor： MARTIN ALEXANDRE ,  VILLANUEVA DAVY ,  SALVETTI FREDERIC

IPC: H01L21/76 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088

CPC classification number: H01L21/764

Abstract: PROBLEM TO BE SOLVED: To acquire a hollow separation groove of a required dimension, particularly the hollow separation groove having large width with a large air capacity.
SOLUTION: A method of manufacturing an integrate circuit is provided, including a preparation of a hollow separation groove in a substrate and generation of an active component in and on an active region of the substrate located between grooves. The preparation of the hollow separation groove includes an initial processing stage performed before the generation of the active component and after the generation of the active component. The initial stage includes a formation of grooves in the substrate and a filling of the grooves with a filling material, and the final processing stage includes an encapsulation of the active component, the preparation of an access passage to each of the filled hollow separation grooves through the material of the encapsulation, removing of the filling material through each of the access passages, and plugging of an opening part of each of the hollow separation grooves through corresponding access passage.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了获得所需尺寸的中空分隔槽，特别是具有大空气容量的宽度大的中空分离槽。 提供了一种制造集成电路的方法，包括在衬底中制备中空分隔槽并在位于沟槽之间的衬底的有源区中及其有源区上产生有源成分。 中空分离槽的制备包括在生成有源成分之前和生成有源成分之后进行的初始处理阶段。 初始阶段包括在衬底中形成凹槽并用填充材料填充凹槽，并且最后的处理阶段包括活性组分的包封，将准备通道准备到每个填充的中空分隔槽通过 封装材料，通过每个进入通道去除填充材料，以及通过相应的进入通道堵塞每个中空分隔槽的开口部分。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004206721A

公开(公告)日：2004-07-22

申请号：JP2003425525

申请日：2003-12-22

Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

Inventor： LEHONGRE DENIS

IPC: G06F7/02 ,  G06F7/22 ,  G11B20/14 ,  H03H17/02 ,  H03M5/00 ,  H03M5/04 ,  H03M5/14 ,  H03M7/46

CPC classification number: G06F7/22 ,  G11B20/1426 ,  H03H17/0263 ,  H03M5/00 ,  H03M5/04 ,  H03M5/145 ,  H03M7/46

Abstract: PROBLEM TO BE SOLVED: To reduce an operation time in the case of processing a large number of data.
SOLUTION: This device is a digital data processor, more specifically, a device for reading the maximum value or the minimum value of data belonging to a set of 2
n codes, an order relation is established and each code has a rank R constituted of 0 to 2
n -1, respectively in the set. The device is a conversion circuit for each piece of digital data processed for generating the conversion of binary digits constituted of 2
n binary elements T[x] having X=1 to 2
n -1, T[2
n -1]T[2
n -2] T[x] to T[2] T[1] and is provided with the one in which T(x)=0 when X is absolutely larger than R and T(x)=1 when X is smaller than or equal to R here. The circuit for executing digital processing receives the result of this conversion.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：在处理大量数据的情况下减少操作时间。 解决方案：该设备是数字数据处理器，更具体地，用于读取属于一组2 n 代码的数据的最大值或最小值的设备，建立了顺序关系 并且每个代码分别具有由0到2 n -1构成的秩R。 该装置是用于产生由具有X = 1至2 n n 个二进制元素T [x]构成的二进制数字的转换的每个数字数据的转换电路。 > -1，T [2 n -1] T [2 n -2] T [x]到T [2] T [1] 当X小于或等于R时，当X绝对大于R且T（x）= 1时，T（x）= 0。 用于执行数字处理的电路接收该转换的结果。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004046824A

公开(公告)日：2004-02-12

申请号：JP2003157411

申请日：2003-06-03

Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

Inventor： MANI CHRISTOPHE

IPC: G06K19/07 ,  G06K7/00 ,  G06K17/00 ,  H04B5/02

CPC classification number: G06K7/10029 ,  G06K7/0008

Abstract: PROBLEM TO BE SOLVED: To provide a collision prevention method for identifying and selecting a plurality of non-contact electronic modules by means of a simple structure and to provide the non-contact electronic module. SOLUTION: In advance of communication between a terminal 19 and a plurality of non-contact electronic modules 10, the respective modules 10 generate random identification numbers ID. During a time slot varied according to the identification numbers, the module 10 responds to a general or auxiliary identification request, and the module 10, which is not selected on receipt of the auxiliary identification request PCALL16, generates new random identification number. While the time slot is varied according to this identification number, a time slot of the unselected module 10 complying with the auxiliary identification request is prevented from being equalized to that of the module 10 complying with the previous auxiliary identification request. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004032752A

公开(公告)日：2004-01-29

申请号：JP2003167394

申请日：2003-06-12

Applicant: St Microelectronics Sa ,  Stmicroelectronics Nv ,  エスティマイクロエレクトロニクス エスエー ,  エスティマイクロエレクトロニクス エヌヴィ

Inventor： HELAL DIDIER ,  LEBOWSKY FRITZ

IPC: H04J13/00 ,  H03K7/04 ,  H04L25/49

CPC classification number: H04B1/7174 ,  H03K7/04 ,  H04L25/4902

Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling the transmission of a super-wideband position modulation pulse signal with high precision.
SOLUTION: In this method, a pulse signal is constituted so as to be involved in a time window. A control signal which contains an identification showing the position of a pulse in a corresponding window, in connection with each pulse is provided for a pulse generator. Further, continuous groups of N bits which coordinately define a digital sign showing the position of a pulse inside the window are transmitted by transmission frequency (Fe) which is greater than a pulse repetition frequency, regarding the respective time windows. The digital position sign is converted to the control signal which is spread in time along the length of the window and contains the position identification, at a moment corresponding to the digital position sign. As a result, the pulse can be positioned inside the window with a time precision equal to 1/N.Fe.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003273257A

公开(公告)日：2003-09-26

申请号：JP2003057906

申请日：2003-03-05

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： DRAY CYRILLE ,  GENDRIER PHILIPPE ,  FOURNEL RICHARD

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: PROBLEM TO BE SOLVED: To provide a memory device which overcomes the data holding problem caused by the thinness of its grid dielectric present in the interface between its STI-type isolation region and its grid material.
SOLUTION: The semiconductor memory device comprises a non-volatile programmable and electrically erasable memory cell having a single layer of grid material. Also, the memory cell comprises a floating grid transistor and a control grid within an active semiconductor area which is formed in a region of a substrate and is delimited by an isolation region. The single layer of grid material wherein the floating grid is formed extends integrally above the active semiconductor area without overlapping part of the isolation region. The floating grid transistor is electrically isolated from the control grid by PN junctions that are inversely polarized.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种克服由其STI型隔离区域和其栅格材料之间的界面中存在的栅极电介质薄度引起的数据保持问题的存储器件。 解决方案：半导体存储器件包括具有单层栅格材料的非易失性可编程和电可擦除存储单元。 此外，存储单元包括浮动栅极晶体管和在有源半导体区域内的控制栅格，该有源半导体区域形成在衬底的区域中并由隔离区域限定。 其中形成浮栅的单层栅格材料在有源半导体区域上整体地延伸，而不与隔离区的重叠部分重叠。 浮栅晶体管通过PN极点与控制栅极电隔离，反向极化。 版权所有（C）2003，JPO

公开(公告)号：JP2003216584A

公开(公告)日：2003-07-31

申请号：JP2002268352

申请日：2002-09-13

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC

IPC: A61B5/117 ,  G06F21/32 ,  G06K19/10 ,  G06T7/00 ,  G07C9/00 ,  G06F15/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for secured identification by using biometric data and an integrated circuit chip when using an arbitrary function with biometric data. SOLUTION: The digital biometric data obtained by a sensor 1 is combined with identification data (CHIPID) of the integrated circuit chip contained in a device common to the sensor 1. The chip identification data (CHIPID) is obtained from a physical parameter network 17 and is formed to perform secured authentication. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003198528A

公开(公告)日：2003-07-11

申请号：JP2002294697

申请日：2002-10-08

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  BARDOUILLET MICHEL ,  PLAZA LAURENT

IPC: G06K19/10 ,  G07F7/10 ,  H01L23/544 ,  H01L23/58 ,  H04L9/08 ,  H04L9/10

Abstract: PROBLEM TO BE SOLVED: To provide a method for generating secret quantities by an integrated circuit according to the destination of these secret quantities. SOLUTION: In a method and a circuit for generating several secret quantities by the integrated circuit according to the destination of these secret quantities, a first digital ward forming a single identifier of the integrated circuit chip and coming from a physical parameter network is taken into account and this identifier is individualized according to an application. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002335138A

公开(公告)日：2002-11-22

申请号：JP2002082748

申请日：2002-03-25

Applicant: ST MICROELECTRONICS SA

Inventor： GARCIA PATRICE ,  BELOT DIDIER

IPC: H03G3/10 ,  H03G1/00 ,  H04B1/40 ,  H04M1/00 ,  H04M1/725

Abstract: PROBLEM TO BE SOLVED: To provide an amplifier device having a gain switching and a radio- frequency receiver integrating thereinto, such an amplifier device where its output dynamic range is optimized in its 'low-gain' mode, while maintaining high gain in its 'high-gain' mode. SOLUTION: The amplifier device with a gain switching comprises an amplification means (Q1); a configurable load circuit (M1, M2) including an inductive element (L2) and capable of exhibiting two different configurations, having two different impedance values respectively; and a controllable switching means (Q2, Q3) connected between the amplification means and the load circuit, in order to select one or other of the two configurations of the load circuit. The load circuit includes two insulated-gate field-effect transistors (M1, M2), connected in series and operating in a triode mode and includes the inductive element, connected in parallel with the pair of load transistors between a power- supply terminal and the switching means.

公开(公告)号：JP2002328834A

公开(公告)日：2002-11-15

申请号：JP2002046868

申请日：2002-02-22

Applicant: ST MICROELECTRONICS SA

Inventor： BAHOUT YVON

IPC: G11C11/413 ,  G06F12/02 ,  G11C8/04 ,  G11C11/41

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device with extremely high speed address jump and to sequentially read contents from its memory. SOLUTION: This invention is of the method for sequentially reading the contents from the memory (10) by using an increment type address counter (12). To jump an address, (a) an address jump signal is detected, (b) the increment type address counter (12) is made incremental, (c) the contents of the memory (10) are read by the address made incremental, (d) the contents read by the address made incremental are written in the increment type address counter (12) and (e) the contents of the memory (10) are read by the address included in the increment type address counter (12).

公开(公告)号：JP2002270812A

公开(公告)日：2002-09-20

申请号：JP2001146544

申请日：2001-05-16

Applicant: ST MICROELECTRONICS SA

Inventor： MATHIEU ROY

IPC: H01L21/331 ,  H01L23/31 ,  H01L29/06 ,  H01L29/417 ,  H01L29/732 ,  H01L29/74

Abstract: PROBLEM TO BE SOLVED: To provide the peripheral structure of a power component resisting a high voltage. SOLUTION: A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region, that does not extend to the component periphery, the high voltage being capable of existing between the first and second regions and having to withstand the junctions between the first and second regions and the substrate. A deep insulating region 31 that does not join the first region 3 is provided at the lower periphery of the component. The lower surface of the substrate between the deep insulating region and the first region is coated with an insulating-layer. The height of the deep insulating region is greater than the upward extension of soldering 22, formed during the soldering of the lower surface on a heat sink.