公开(公告)号：JP2539899B2

公开(公告)日：1996-10-02

申请号：JP28870188

申请日：1988-11-15

Applicant: TANDEM COMPUTERS INC

Inventor： OORANGUZEBU KEI KAAN

IPC: H03K19/003 ,  H03K19/018

公开(公告)号：JPH0866015A

公开(公告)日：1996-03-08

申请号：JP16185995

申请日：1995-06-28

Applicant: TANDEM COMPUTERS INC

Inventor： DEIBUITSUDO ERU OORUDORITSUJI ,  SUTEIIBUN AARU BIISERU ,  DANIERU DEII GAN

IPC: G06F1/26 ,  G05F1/10 ,  G06F1/18 ,  G06F1/30 ,  G06F11/00 ,  H02H3/05 ,  H02H9/00 ,  H02J1/10 ,  H02M3/00

Abstract: PURPOSE: To protect a logical unit circuit from the transient state of power and power fluctuation by changing over power-supply inputs from alternating power supplies. CONSTITUTION: First and second enable circuits 40, 50 generate signals which select whether or not power is supplied from first and/or second power supplies 20, 30. First and second inrush limiters 60, 70 limit the time change rate of a current flowed through a DC converter 120, in response to the enable signals. First and second open circuits 80, 90 connect the first and second inrush limiters 60, 70 and the DC converter 120 to the first and second enable circuits 40, 50, when the circuits 80, 90 are connected to first and second pair short-circuit pins 73, 83. The first and second pair short-circuit pins 73, 83 are conjoined with the first and second open circuits 80, 90 respectively when a logical unit 10 is inserted completely to a computer housing, but the short-circuit pins 73, 83 are not connected, when the logical unit 10 is not completely inserted into the computer housing.

公开(公告)号：JPH0863262A

公开(公告)日：1996-03-08

申请号：JP16171195

申请日：1995-06-28

Applicant: TANDEM COMPUTERS INC

Inventor： DANIERU DEII GAN ,  UIRIAMU PATAASON BANTON

IPC: G06F1/20 ,  G05B9/03 ,  G06F11/00

Abstract: PURPOSE: To provide a fan assembly fault tolerant control/monitor system which is applied to a computer system and can reduce the probability of high temperature breakage. CONSTITUTION: This system is used to an electronic device and provided with a power mixture circuit 106 which supplies the duplicate power to a fan to reduce the probability of high temperature breakage due to a power fault. Then the system includes a means which detects the fault of the circuit 106, a means which measures the accurate speed of the fan, and a means which can perform the fine control of the fan speed. The physical existence of a fan unit 118 can be detected with no request given for addition of pins.

公开(公告)号：JPH06242887A

公开(公告)日：1994-09-02

申请号：JP26344692

申请日：1992-10-01

Applicant: TANDEM COMPUTERS INC

Inventor： MAAKU UOOKAA ,  ARUBAATO ESU RUI ,  HARARUDO SAMAA ,  UIN EMU CHIYAN ,  UIRIAMU TEII FURAA

IPC: G06F11/18 ,  G06F9/52 ,  G06F15/173 ,  G06F3/06 ,  G06F15/16

Abstract: PURPOSE: To provide a computer system which can secure the optimum matching between the I/O band width of a data storage array system and the I/O performance of a CPU. CONSTITUTION: A plurality of CPU1 are freely and directly connected to a plurality of disk arrays 4 via a switching network. Thus, it is possible to make up such a computer system that can secure the optimum matching between the I/O band width of every array 4 and the I/O performance of every CPU1 by connecting these array and CPU together using the switching network.

公开(公告)号：JPH06208476A

公开(公告)日：1994-07-26

申请号：JP857893

申请日：1993-01-21

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU TEII FURAA

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/08 ,  G06F12/16

Abstract: PURPOSE: To improve the characteristics of a storing subsystem by suppressing the number of performing times of access to a required storage unit so as to improve the I/O characteristic of a redundant storage array system. CONSTITUTION: A redundant array parity caching system is provided with an RRR-parity cache 5 and a controller 3 which discriminates RRR-parity blocks and caches the cache 5. The RRR-parity block is equal to the exclusive OR of an old data block and an old parity block read out from a line having the same redundancy as that the old data block has. When the RRR-parity block is cached, therefore, the action of a write-intensive storage unit can be reduced by three I/O accessing times in maximum.

公开(公告)号：JPH0695757A

公开(公告)日：1994-04-08

申请号：JP908991

申请日：1991-01-29

Applicant: TANDEM COMPUTERS INC

Inventor： CHIERIIRO RINO KONSUTANCHINO ,  DEIBUITSUDO PII CHIENGUSON ,  DATSUKU ENU RII ,  ROODOSON ERU YUU ,  AURANGUZEBU KEI KAAN

IPC: G06F1/12 ,  G06F1/10 ,  H03K5/00

Abstract: PURPOSE: To maintain a synchronous state for a long time by tracing a reference signal regardless of temperature, voltage and process fluctuations and therefore generating plural clock signals which synchronize with a reference clock. CONSTITUTION: A processor unit 12 which operates in response to clock signals that are given from a clock generator 14 generates various control signals which are sent to a control/controlled logic 18 via a multiple signal line bus 16. On the other hand, the unit 12 generates a periodic clock signal (SYSOUT) and sends it to a clock synchronizer 20 as a reference system clock. The synchronizer 20 receives the clock signal from the generator 14 and generates many clock signals (SYSCLK-OUT) serving as the synchronous replicas of the SYSOUT. These clock signals are sent to the logic 18 and perform the clocking and synchronous functions of a circuit which is included in the logic 18.

公开(公告)号：JPH05346866A

公开(公告)日：1993-12-27

申请号：JP31468492

申请日：1992-11-25

Applicant: TANDEM COMPUTERS INC

Inventor： ARUBAATO RUI ,  MAAKU ESU UOOKAA

IPC: G06F3/06 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F12/06 ,  G11C29/00

Abstract: PURPOSE: To establish the completion and maintenance of a data changing operation to a redundant array data storage system, and to establish the maintenance of redundancy in the system. CONSTITUTION: A check point is applied to an operation. After the completion of a buffer provided at a reliability host processing formed of main and second CPU 1a and 1b, written data in host CPU adapters 2a and 2b are blocked by a buffer 11 before the data are transmitted to array controllers 3a and 3b so that the completion of a data changing operation can not be disturbed by the fault of the CPU 1a and 1b. A reliability array processing is formed of the main and second array controllers 3a and 3b. A storage device 4 provided with the array controllers 3a and 3b and a storage array is backed up by a power battery. All data changing operation command information is stored by the non-volatile memory of an array controller for data records which are not sufficiently written in the storage devise 4 in order to prepare for the following retry.

公开(公告)号：JPH053941B2

公开(公告)日：1993-01-18

申请号：JP24038484

申请日：1984-11-14

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU AARU GUTSUDOMAN ,  RICHAADO BII MEIFUIIRUDO ,  TETSUDO TAUSHUNSUKII ,  FUREDORITSUKU ERU ZARUDEIATSUKASU

IPC: G06F11/00 ,  G06F13/00 ,  G06F13/42 ,  H04L1/16 ,  H04L1/18 ,  H04L29/08

Abstract: The present disclosure relates to a communications method for communicating data over a data channel that comprises two unidirectional communication lines. A protocol which is a set of predetermined control characters is used by the communications method and the protocol is used for transferring data between communicating devices. The communications method combines acknowledgments which are control characters of the protocol transmitted in between messages, piggy-backing which is the combining of control characters of the protocol and data messages, and hold-offs with long time outs which cause the devices to enter a standby idle mode waiting for a responsive control character of the protocol. The communications system and method combines these features so as to permit improved efficient flow control of data information between the communicating devices.

公开(公告)号：JPH0425580B2

公开(公告)日：1992-05-01

申请号：JP719983

申请日：1983-01-19

Applicant: TANDEM COMPUTERS INC

Inventor： RICHAADO ANSONII HANFURII ,  SUTEIIUN DERITSUKU FUITSUSHAA ,  SUTEIIUN UOOREN UIIRENGA ,  JON SUJOSUTETSUDO

IPC: G06F12/00 ,  G06F11/00 ,  G06F11/10 ,  G06F11/30 ,  G06F12/16 ,  G11C29/02

公开(公告)号：JPH0382973A

公开(公告)日：1991-04-08

申请号：JP12807490

申请日：1990-05-17

Applicant: TANDEM COMPUTERS INC

Inventor： JIYON EI BURATSUKAN

IPC: G01R31/02 ,  G06F11/08 ,  G06F11/30 ,  H04B3/46

Abstract: PURPOSE: To improve the method and device so that the quantity of hardware and circuit delay are minimized by inputting the N signal lines to leaf nodes in pairs and composing of branch parts of tree constitution of general nodes of integer level. CONSTITUTION: Two signals are generated by each of the leaf nodes 12a to 12d to which the N signal lines are inputted in pairs. It is stated that a scene signal S is active when at least one of the input signals is active and an error signal E is active when only one signal is active. Those are inputted to the general nodes 24 of integer level. Each node has four input parts and two output parts for the signals S and N, which are inputted to next levels in order to reach two nodes 26a and 26b, whose outputs 20c and 20d, and 22c and 22d are inputted to two pairs of S and E input parts of a root node 28. They are compared to generate an output 30. Consequently, a signal line can be added with minimum trouble by the simple pyramid structure designing.