公开(公告)号：KR1020100055867A

公开(公告)日：2010-05-27

申请号：KR1020080114755

申请日：2008-11-18

Applicant: 삼성전자주식회사

Inventor： 김경국 ,  채수희 ,  박영수 ,  김택 ,  양문승 ,  정형수 ,  박재철 ,  김준연

IPC: H01L33/12 ,  H01L33/02

CPC classification number: H01L33/0079 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A method for manufacturing a light emitting display is provided to reduce manufacturing costs of the light emitting device by performing a manufacturing process of the light emitting device at once after connecting several growth substrates on a bonding substrate with a large area. CONSTITUTION: A semiconductor layer with an active area for emission is formed on a growth substrate(11). A plurality of growth substrates with respective semiconductor layers are arranged on one bonding substrate(30). The plurality of semiconductor layers respectively formed on the plurality of growth substrates are simultaneously processed through a post-process. The surface of the growth substrate faces the bonding substrate and the growth substrate is bonded on the bonding substrate.

Abstract translation: 目的：提供一种制造发光显示器的方法，通过在大面积的接合基板上连接多个生长基板之后，一次进行发光器件的制造工艺来降低发光器件的制造成本。 构成：在生长衬底（11）上形成具有用于发射的有源区的半导体层。 具有各个半导体层的多个生长衬底被布置在一个接合衬底（30）上。 分别形成在多个生长衬底上的多个半导体层通过后处理同时进行处理。 生长衬底的表面面向接合衬底，生长衬底接合在接合衬底上。

公开(公告)号：KR1020090103610A

公开(公告)日：2009-10-01

申请号：KR1020080029327

申请日：2008-03-28

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  박영수 ,  박재철

IPC: H01L27/04 ,  H01L29/786

CPC classification number: H01L21/823462 ,  H01L21/84 ,  H01L27/0883 ,  H01L27/1225

Abstract: PURPOSE: An inverter is provided to perform an existing CMOS inverter property and to simplify a manufacturing process. CONSTITUTION: An inverter includes a depletion mode load transistor(T1), an enhancement mode driving transistor(T2), and a barrier layer. The depletion mode load transistor has a first oxide layer as a channel layer. The enhancement mode driving transistor is connected to the load transistor, and has a second oxide layer as a channel layer. The barrier layer is formed between a source electrode and a drain electrode corresponding to the second oxide layer.

Abstract translation: 目的：提供逆变器来执行现有的CMOS反相器特性，并简化制造过程。 构成：逆变器包括耗尽型负载晶体管（T1），增强型驱动晶体管（T2）和阻挡层。 耗尽型负载晶体管具有作为沟道层的第一氧化物层。 增强型驱动晶体管连接到负载晶体管，并具有作为沟道层的第二氧化物层。 在与第二氧化物层对应的源电极和漏电极之间形成阻挡层。

公开(公告)号：KR1020090096151A

公开(公告)日：2009-09-10

申请号：KR1020080021563

申请日：2008-03-07

Applicant: 삼성전자주식회사

Inventor： 이현웅 ,  박재철 ,  이헌수 ,  염윤호

IPC: H01L23/02

Abstract: A chip device comprising a changeable mask and a method of manufacturing a chip device are provided to prevent the increase of manufacturing cost and period in changing product information by using a variable mask. In a chip device comprising a changeable mask and a method of manufacturing a chip device, a power line delivers power voltage. A reference voltage line delivers the reference voltage, and a power connection node is connected to the power line. A reference access node is connected to the reference voltage line, and an information metal pattern is connected to the reference access node through a reference via contact. The information metal pattern is formed on one specific layer among a plurality of layers.

Abstract translation: 提供了包括可变掩模的芯片装置和制造芯片装置的方法，以防止通过使用可变掩模来改变产品信息的制造成本和周期的增加。 在包括可变形掩模的芯片装置和制造芯片装置的方法中，电力线传送电力电压。 参考电压线提供参考电压，电源连接节点连接到电源线。 参考接入节点连接到参考电压线，并且信息金属图案通过参考经由接触连接到参考接入节点。 信息金属图案形成在多个层中的一个特定层上。

公开(公告)号：KR1020080114357A

公开(公告)日：2008-12-31

申请号：KR1020070063826

申请日：2007-06-27

Applicant: 삼성전자주식회사

Inventor： 김선일 ,  송이헌 ,  박영수 ,  강동훈 ,  김창정 ,  박재철

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: A thin film transistor is provided to obtain a high switching characteristic and increase an operation speed by using a transition metal doped IZO layer as a channel layer of the thin film transistor. A thin film transistor includes a gate electrode(140), a channel layer(110), a source electrode(120a) and a drain electrode(120b). The gate electrode and the channel layer are formed to interpose a gate insulating layer. The source electrode and the drain electrode are contacted with both ends of the channel layer. The channel layer includes the transition metal doped IZO(Indium Zinc Oxide).

Abstract translation: 提供薄膜晶体管以获得高开关特性，并且通过使用掺杂过渡金属的IZO层作为薄膜晶体管的沟道层来提高操作速度。 薄膜晶体管包括栅电极（140），沟道层（110），源电极（120a）和漏电极（120b）。 形成栅电极和沟道层以插入栅极绝缘层。 源电极和漏电极与沟道层的两端接触。 沟道层包括掺杂过渡金属的IZO（氧化铟锌）。

公开(公告)号：KR1020080106148A

公开(公告)日：2008-12-04

申请号：KR1020080104272

申请日：2008-10-23

Applicant: 삼성전자주식회사

Inventor： 박재철 ,  김창정 ,  김선일 ,  송이헌 ,  박영수

IPC: H01L29/786 ,  G02F1/136

CPC classification number: H01L29/78693 ,  H01L29/458

Abstract: A thin film transistor is provided to increase the stability and secure the device characteristic without the compensating circuit by forming the source and drain with the conductive oxide materials and the metal layer with low resistance. A thin film transistor comprises the gate(42), the gate isolation layer(44), the channel layer(46), the source(52a), and the drain(52b). The gate isolation layer is contacted with the gate. The channel layer is contacted with the gate isolation layer. The channel layer is in opposite directions to the gate. The gate isolation layer is positioned between the channel layer and the gate. The source is contacted with one end of the channel layer. The drain is contacted with the other end of the channel layer. The channel layer is the amorphous oxide semiconductor layer. The source and the drain are formed by including the conductive oxide layer and the metal layer with low resistance.

Abstract translation: 提供薄膜晶体管以通过用导电氧化物材料和具有低电阻的金属层形成源极和漏极来增加稳定性并且确保器件特性而不需要补偿电路。 薄膜晶体管包括栅极（42），栅极隔离层（44），沟道层（46），源极（52a）和漏极（52b）。 栅极隔离层与栅极接触。 沟道层与栅极隔离层接触。 沟道层与栅极相反。 栅极隔离层位于沟道层和栅极之间。 源与通道层的一端接触。 漏极与沟道层的另一端接触。 沟道层是非晶氧化物半导体层。 源极和漏极通过包括导电氧化物层和具有低电阻的金属层而形成。

公开(公告)号：KR1020080094300A

公开(公告)日：2008-10-23

申请号：KR1020070038537

申请日：2007-04-19

Applicant: 삼성전자주식회사

Inventor： 박재철 ,  김창정 ,  김선일 ,  송이헌 ,  박영수

IPC: H01L29/786 ,  G02F1/136

CPC classification number: H01L29/78618 ,  H01L29/78621 ,  H01L29/7869 ,  H01L29/78693

Abstract: A thin film transistor is provided to guarantee a uniformity characteristic of a flat panel display by using a thin film transistor in a flat panel display like an LCD(liquid crystal display) or an OLED(organic light emitting diode) wherein the channel layer of the thin film transistor is an amorphous oxide semiconductor layer. A gate insulation layer(44) comes in contact with a gate. A channel layer(46) confronts the gate wherein the gate insulation layer is positioned between the gate and the channel layer, coming in contact with the gate insulation layer. A source(52a) comes in contact with one end of the channel layer. A drain(52b) comes in contact with the other end of the channel layer. The channel layer is an amorphous oxide semiconductor layer. The source and the drain are a conductive oxide layer in which predetermined conductive impurities are included in an oxide semiconductor layer. Low resistance metal layers can be formed on the source and the drain. The gate can be formed on or under the channel layer.

Abstract translation: 提供薄膜晶体管以通过在诸如LCD（液晶显示器）或OLED（有机发光二极管）的平板显示器中使用薄膜晶体管来保证平板显示器的均匀性特性，其中， 薄膜晶体管是非晶氧化物半导体层。 栅极绝缘层（44）与栅极接触。 沟道层（46）面对栅极，其中栅极绝缘层位于栅极和沟道层之间，与栅极绝缘层接触。 源（52a）与沟道层的一端接触。 漏极（52b）与沟道层的另一端接触。 沟道层是非晶氧化物半导体层。 源极和漏极是在氧化物半导体层中包含预定导电杂质的导电氧化物层。 低电阻金属层可以形成在源极和漏极上。 栅极可以形成在沟道层上或下面。