公开(公告)号：WO1997013193A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015417

申请日：1996-10-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FAVOR, John, G.

IPC: G06F09/30

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3853

Abstract: Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction source and determining the starting point of each instruction so that multiple instructions are presented to a decoder simultaneously for decoding in parallel. Immediately upon accessing the multiple variable-length instructions from an instruction memory, a predecoder derives predecode information for each byte of the variable-length instructions by determining an instruction length indication for that byte, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoder associates an instruction length to each instruction byte. The instructions and predecode information are applied to an instruction buffer circuit in a memory-aligned format. The instruction buffer circuit prepares the variable-length instructions for decoding by converting the instruction alignment from a memory alignment to an instruction alignment on the basis of the instruction length indication. The instruction buffer circuit also assists the preparation of variable-length instructions for decoding of multiple instructions in parallel by facilitating a conversion of the instruction length indication to an instruction pointer.

Abstract translation: 准备可变长度指令，以通过从指令源读取多个可变长度指令并且确定每个指令的起始点来并行地同时解码和执行多个指令，以便同时向解码器呈现多个指令以进行解码 平行。 在从指令存储器访问多个可变长度指令时，预解码器立即通过确定该字节的指令长度指示来导出可变长度指令的每个字节的预解码信息，假设每个字节作为操作码字节，因为实际操作码 字节未被识别。 预解码器将指令长度与每个指令字节相关联。 指令和预解码信息以存储器对准的格式应用于指令缓冲器电路。 指令缓冲器电路根据指令长度指示，通过将指令对准从存储器对准转换为指令对准来准备用于解码的可变长度指令。 指令缓冲器电路还通过促进将指令长度指示转换为指令指针来协助准备用于并行解码多个指令的可变长度指令。

公开(公告)号：WO1997011488A1

公开(公告)日：1997-03-27

申请号：PCT/US1996013931

申请日：1996-08-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  STOLMEIJER, Andre

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/768 ,  H01L21/76807 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel interconnect layout method and metallization scheme is provided. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers (32, 36) stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other.

Abstract translation: 提供了一种新颖的互连布局方法和金属化方案。 本发明的方法提供了仅由堆叠在彼此顶部的图案化金属层（32,36）形成的多层互连结构。 可以使用图案化的金属互连作为构建块来形成沿着水平路径形成电连接的两条互连线以及沿垂直路径形成电连接的触点。 为了形成较厚的金属层用于构造厚的互连线，两个或多个图案化的金属层可以彼此堆叠。

公开(公告)号：WO1997010614A1

公开(公告)日：1997-03-20

申请号：PCT/US1996013033

申请日：1996-08-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BUI, Nguyen, Duc ,  WOLLESON, Donald, L.

IPC: H01L23/532

CPC classification number: H01L23/528 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line or providing longitudinally spaced apart holes or vias to optimize the backflow potential capacity of the metal interconnection line. In addition, elongated slots are formed through the metal interconnection line so that the total width of metal across the interconnection line is selected for optimum electromigration lifetime in accordance with the Bamboo Effect for that metal.

Abstract translation: 金属互连线的电迁移寿命通过调整互连线的长度或提供纵向间隔开的孔或通孔来增加，以优化金属互连线的回流势能。 此外，通过金属互连线形成细长的槽，使得根据该金属的竹效应，选择跨越互连线的金属的总宽度以获得最佳的电迁移寿命。

公开(公告)号：WO1997008872A1

公开(公告)日：1997-03-06

申请号：PCT/US1996011615

申请日：1996-07-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LEE, Dennis ,  FISCHER, Matthew

IPC: H04L12/28

CPC classification number: H04L29/06 ,  H04L2212/00 ,  H04W74/00 ,  H04W80/02 ,  H04W84/12 ,  H04W88/06

Abstract: A system and method for providing a flexible medium access control device (32). The medium access control (MAC) device includes four configurable transmit and receive modes for communicating with a physical layer signaling control device. The four modes are controlled by a processor (36) and a transceiver interface (38). In operation, the modes enable the MAC device to transmit and receive MAC data to and from the physical layer signaling control device, and to optionally transmit and receive PHY data to and from the physical layer signaling control device, thereby providing compatibility between a MAC device and a radio (34), regardless of the physical layer functionality of the radio.

Abstract translation: 一种用于提供柔性介质访问控制设备（32）的系统和方法。 介质访问控制（MAC）设备包括用于与物理层信令控制设备通信的四个可配置的发送和接收模式。 这四种模式由处理器（36）和收发器接口（38）控制。 在操作中，这些模式使得MAC设备能够向物理层信令控制设备发送和接收MAC数据，并且可选地向物理层信令控制设备发送和接收PHY数据，从而提供MAC设备之间的兼容性 和无线电（34），无论无线电的物理层功能如何。

公开(公告)号：WO1997007409A1

公开(公告)日：1997-02-27

申请号：PCT/US1995014349

申请日：1995-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BREHMER, Geoffrey, E. ,  SCHNIZLEIN, Paul, G.

IPC: G01R19/165

CPC classification number: H03K19/018585 ,  G01R19/16528 ,  G01R19/16538 ,  G05F1/465 ,  G10H7/004 ,  G10H2230/035 ,  G10H2240/275

Abstract: A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive. An input buffer is also described which is configurable depending on whether a 5.0 or 3.3 volt supply voltage is present. The input buffer includes two input buffer circuits. The output of a first input buffer circuit is output as valid data when VCC equals 5.0 volts. The output of the second input buffer circuit is output as valid data when VCC equals 3.3 volts.

Abstract translation: 描述了一种电源电压检测电路，其生成指示VCC的状态为5.0或3.3伏的控制信号。 该控制信号用于产生由音频处理集成电路中的A / D和/或D / A电路使用的模拟参考信号，以及用于控制时钟频率或电流驱动的其它电路。 还描述了可以根据是否存在5.0或3.3V电源电压来配置的输入缓冲器。 输入缓冲器包括两个输入缓冲电路。 当VCC等于5.0伏时，第一输入缓冲电路的输出作为有效数据输出。 当VCC等于3.3V时，第二输入缓冲电路的输出作为有效数据输出。

公开(公告)号：WO1997005655A1

公开(公告)日：1997-02-13

申请号：PCT/US1996012527

申请日：1996-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LIU, Youjuang, W. ,  HADDAD, Sameer, S.

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L29/7885

Abstract: A strip of a semiconductor material (for example, P type silicon) is oxidized and the resulting strip of oxide is removed leaving a depression in the upper surface of the semiconductor material which has steep sidewalls. The steep sidewalls do not have significant ion impact damage because they are formed by oxidation and not by reactive ion etching of the semiconductor material. A high quality tunnel oxide (115) can therefore be grown on the steep sidewalls. Floating gates (123-132) are then formed on the tunnel oxide (115), corresponding word lines are formed over the floating gates, a conductive region (114) (for example, N type silicon) is formed into the bottom of the depression, and a number of conductive regions (150) (for example, N type silicon) corresponding with the floating gates are formed above the rim of the depression. The resulting bit transistors have channel regions which extend in a vertical dimension under floating gates along the surface ofthe sidewall. Because the depth and profile of the depression is determined primarily by oxidation and not by lithography, very small geometry bit transistors can be made.

Abstract translation: 半导体材料（例如P型硅）的条被氧化，并且所得到的氧化物条被去除，留下具有陡峭侧壁的半导体材料的上表面的凹陷。 陡峭的侧壁不具有显着的离子冲击损伤，因为它们是通过氧化而不是通过半导体材料的反应离子蚀刻形成的。 因此，可以在陡峭的侧壁上生长高质量的隧道氧化物（115）。 然后在隧道氧化物（115）上形成浮动栅极（123-132），在浮动栅极上形成对应的字线，将导电区域（114）（例如，N型硅）形成在凹陷的底部 并且在凹部的边缘的上方形成有与浮动栅极对应的多个导电区域（150）（例如，N型硅）。 所产生的位晶体管具有沿着侧壁表面的浮动栅极沿垂直尺寸延伸的沟道区。 由于凹陷的深度和轮廓主要由氧化而不是通过光刻确定，所以可以制造非常小的几何位晶体管。

公开(公告)号：WO1997005497A1

公开(公告)日：1997-02-13

申请号：PCT/US1996012533

申请日：1996-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TSIANG, Jerry ,  LANTZ, Mikkel ,  PENG, Yeng-Kaung ,  SHIAU, Ying

IPC: G01R31/28

CPC classification number: G01R31/31903 ,  G01R31/2831 ,  G01R31/2834 ,  G01R31/2851

Abstract: Methods and apparatus are disclosed for testing integrated circuits at the wafer level and for integrating test results, calculation of lifetimes and generation of trend charts in a common data base following testing. A wafer tester controller is supplemented with additional hardware and software to avoid data transfer errors and facilitate processing and storage of test results. The data base is available over a network to all areas of an organization.

Abstract translation: 公开了用于在晶片级测试集成电路并且用于在测试之后的通用数据库中集成测试结果，寿命计算和趋势图的生成的方法和装置。 晶圆测试仪控制器补充有额外的硬件和软件，以避免数据传输错误，便于处理和存储测试结果。 数据库可通过网络提供给组织的所有区域。

公开(公告)号：WO1996042141A1

公开(公告)日：1996-12-27

申请号：PCT/US1996009994

申请日：1996-06-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHARPE-GEISLER, Bradley, A.

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17704

Abstract: An FPGA including SRAM memory cells (400), each having a latch configured so that both read and write signals are provided through the data path connection. By providing both read and write through the data path, the FPGA further includes only a single decoder to control pass gates connected to the memory cells (400) during read and write. To prevent voltages during write from damaging pass gates in the data path, the FPGA further includes a modified power supply to provide voltages ranging from VDD to VSS to the memory cell transistors (414, 416, 418, 420) during read, while providing a reduced voltage range during write to enable memory cell states to more easily be altered.

Abstract translation: 一种包括SRAM存储单元（400）的FPGA，每个存储单元具有被配置为使得通过数据路径连接提供读取和写入信号的锁存器。 通过提供通过数据路径的读取和写入，FPGA进一步仅包括单个解码器，以在读取和写入期间控制连接到存储器单元（400）的通过门。 为了防止写入期间的电压在数据路径中的损坏的通过栅极，FPGA还包括修改的电源，以在读取期间向VDD到VSS提供电压到存储单元晶体管（414,416,418,420），同时提供一个 在写入期间降低电压范围以使存储单元状态更容易被改变。

公开(公告)号：WO1996039657A1

公开(公告)日：1996-12-12

申请号：PCT/US1996008635

申请日：1996-06-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KRANICH, Uwe

IPC: G06F09/38

CPC classification number: G06F9/382 ,  G06F9/3804 ,  G06F12/0862

Abstract: An apparatus and method for reducing the time required to supply a processor core with instructions uses a cache memory, a cache controller, and an instruction predecoding unit. When a line of instructions is retrieved into the cache memory, the instruction predecoding unit inspects the instructions in the line to determine if the line contains any non-sequential instructions. The cache controller stores an indication of whether the line contains non-sequential instructions with the line of instructions in the cache memory. If a given line of instructions does not contain any non-sequential instructions, the line of instructions following the given line is retrieved into the cache memory when one of the instructions in the given line is requested by the processor core.

Abstract translation: 用于减少向处理器核提供指令所需的时间的装置和方法使用高速缓冲存储器，高速缓存控制器和指令预解码单元。 当一行指令被检索到高速缓冲存储器中时，指令预解码单元检查该行中的指令以确定该行是否包含任何非顺序指令。 高速缓存控制器存储指示该线是否包含高速缓冲存储器中的指令行的非顺序指令。 如果给定的指令行不包含任何非顺序指令，则当处理器核心请求给定行中的指令之一时，跟随给定行的指令行被检索到高速缓冲存储器中。

公开(公告)号：WO1996038949A1

公开(公告)日：1996-12-05

申请号：PCT/US1996004663

申请日：1996-04-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LO, William ,  CRAYFORD, Ian

IPC: H04L12/22

CPC classification number: H04L63/02 ,  H04L12/22 ,  H04L12/44 ,  H04L12/4625

Abstract: A secure repeater (20) implementing data packet masking includes a programmable and selective, on a per port basis, disrupt response responsive to any of several selectable qualifying conditions. A disrupt controller (70) receives signals indicating various characteristics of fields of a data packet, and other conditions. A register bank (76) includes a plurality of memories, one associated with each port and some of the conditions, assists the disrupt controller to determine the associated port's disrupt response to the data packet. Each memory stores a disrupt control code. When the disrupt control code for a particular port has a value indicating that the associated port is enabled, deassertion of a condition signal associated with that control code results in disruption of a data packet. A cell array (200) permits simple, efficient scaling and formation of integrated semiconductor structures to implement complex disrupt logic equations.

Abstract translation: 实现数据分组屏蔽的安全中继器（20）包括在每个端口基础上的可编程和选择性响应于若干可选择的条件条件中的任何一个的中断响应。 中断控制器（70）接收指示数据分组的各种特性的信号以及其他条件。 寄存器组（76）包括多个存储器，一个与每个端口相关联的存储器和一些条件，帮助中断控制器确定相关端口对数据包的中断响应。 每个存储器存储中断控制代码。 当特定端口的中断控制代码具有指示相关端口被使能的值时，与该控制代码相关联的条件信号的取消取消导致数据分组的中断。 单元阵列（200）允许简单，有效地缩放和形成集成半导体结构以实现复杂的中断逻辑方程。