公开(公告)号：IT8920624D0

公开(公告)日：1989-05-24

申请号：IT2062489

申请日：1989-05-24

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：DK189589D0

公开(公告)日：1989-04-19

申请号：DK189589

申请日：1989-04-19

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G06F12/00 ,  G06F13/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：DK189489D0

公开(公告)日：1989-04-19

申请号：DK189489

申请日：1989-04-19

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

公开(公告)号：NO891583D0

公开(公告)日：1989-04-18

申请号：NO891583

申请日：1989-04-18

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：NO891581D0

公开(公告)日：1989-04-18

申请号：NO891581

申请日：1989-04-18

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G11C11/401 ,  G06F13/362 ,  G11C7/10 ,  G06F

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：FI891787A0

公开(公告)日：1989-04-14

申请号：FI891787

申请日：1989-04-14

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  DEAN MARK EDWARD ,  BLAND PATRICK MAURICE

IPC: G06F9/38 ,  G06F12/08 ,  G06F

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

公开(公告)号：AT31984T

公开(公告)日：1988-01-15

申请号：AT84107801

申请日：1984-07-05

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  BOLT WILLIAM HAWKINS

IPC: H02J1/00 ,  G06F1/00 ,  G06F1/32 ,  G06F3/02 ,  G06F3/023

Abstract: In a self-contained battery powered key entry device, the keyboard (2) is driven from a microprocessor (1) and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter (24). The sense lines (DBO-DB7) are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode. A delay may be incorporated.

公开(公告)号：BR8403982A

公开(公告)日：1985-07-09

申请号：BR8403982

申请日：1984-08-09

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  BOLT WILLIAM HAWKINS

IPC: H02J1/00 ,  G06F1/00 ,  G06F1/32 ,  G06F3/02 ,  G06F3/023

Abstract: In a self-contained battery powered key entry device, the keyboard (2) is driven from a microprocessor (1) and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter (24). The sense lines (DBO-DB7) are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode. A delay may be incorporated.

公开(公告)号：HUT76725A

公开(公告)日：1997-11-28

申请号：HU9701328

申请日：1995-11-27

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  CRONIN DANIEL RAYMOND ,  HOFMANN RICHARD GERARD ,  MOELLER DENNIS ,  VENARCHICK LANCE MICHAEL

IPC: G06F13/28 ,  G06F13/40

公开(公告)号：DE69124905T2

公开(公告)日：1997-09-18

申请号：DE69124905

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  BLAND PATRICK MAURICE ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.