公开(公告)号：BR9505209A

公开(公告)日：1997-09-16

申请号：BR9505209

申请日：1995-11-17

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  CRONIN DANIEL R ,  HOFMANN RICHARD G ,  MOELLER DENNIS ,  VENARCHICK LANCE M

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/36 ,  G06F13/40

Abstract: A computer system that has two buses (30, 32) with different memory addressing capacities and a first bus master (36) that generates M-bit addresses is provided with a bridge (34) between the two buses. In order to generate N-bit addresses for use on the second bus (30), a direct memory access (DMA) controller (50) on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus (30) to address memory (40). The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.

公开(公告)号：HUT76725A

公开(公告)日：1997-11-28

申请号：HU9701328

申请日：1995-11-27

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  CRONIN DANIEL RAYMOND ,  HOFMANN RICHARD GERARD ,  MOELLER DENNIS ,  VENARCHICK LANCE MICHAEL

IPC: G06F13/28 ,  G06F13/40

公开(公告)号：PL320022A1

公开(公告)日：1997-09-01

申请号：PL32002295

申请日：1995-11-27

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  CRONIN DANIEL RAYMOND ,  HOFMANN RICHARD GERARD ,  MOELLER DENNIS ,  VENARCHICK LANCE MICHAEL

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/36 ,  G06F13/40

Abstract: A computer system that has two buses (30, 32) with different memory addressing capacities and a first bus master (36) that generates M-bit addresses is provided with a bridge (34) between the two buses. In order to generate N-bit addresses for use on the second bus (30), a direct memory access (DMA) controller (50) on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus (30) to address memory (40). The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.

公开(公告)号：CA2160499A1

公开(公告)日：1996-05-31

申请号：CA2160499

申请日：1995-10-13

Applicant: IBM

Inventor： BLAND PATRICK M ,  CRONIN DANIEL R III ,  HOFMANN RICHARD G ,  MOELLER DENNIS ,  VENARCHICK LANCE M

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/36 ,  G06F13/40 ,  G06F12/02

Abstract: A computer system that has two buses with different memory addressing capacitiesand a first bus master that generates M-bit addresses is provided with a bridge between the two buses. In order to generate N-bit addresses for use on the second bus, a direct memory access (DMA) controller on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus to address memory. The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.