公开(公告)号：EP1810145A1

公开(公告)日：2007-07-25

申请号：EP05797084.0

申请日：2005-10-25

Applicant: ROBERT BOSCH GMBH

Inventor： KOTTKE, Thomas

IPC: G06F11/16

CPC classification number: G06F11/1695 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/1641 ,  G06F2201/845

Abstract: A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of the system is able to be implemented in which a clock pulse changeover is carried out in at least one processing unit in a switching of the operating mode.

公开(公告)号：EP1807764A2

公开(公告)日：2007-07-18

申请号：EP05803464.6

申请日：2005-10-25

Applicant: ROBERT BOSCH GMBH

Inventor： WEIBERLE, Reinhard ,  MUELLER, Bernd ,  ANGERBAUER, Ralf ,  COLLANI, Yorck ,  GMEHLICH, Rainer ,  BOEHL, Eberhard

IPC: G06F11/16

CPC classification number: G06F11/1641 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3885 ,  G06F11/1654 ,  G06F11/1695 ,  G06F2201/845

Abstract: The invention relates to a method and device for switching over in a computer system having at least two execution units. According to the invention, switching occurs between at least two operating modes, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. The invention is characterized in that the execution units can be connected to an internal bus of the computer system. In the performance mode, at least two execution units are connected to the internal bus and when switching between the performance mode and the comparison mode, at least one execution unit is disconnected from the internal bus by a switch controlled by the changeover switch.

Abstract translation: 本发明涉及一种用于在具有至少两个执行单元的计算机系统中进行切换的方法和设备。 根据本发明，在至少两种操作模式之间进行切换，第一操作模式对应于比较模式，第二操作模式对应于性能模式。 本发明的特征在于执行单元可以连接到计算机系统的内部总线。 在性能模式中，至少两个执行单元连接到内部总线，并且当在性能模式和比较模式之间切换时，通过由转换开关控制的开关将至少一个执行单元从内部总线断开。

公开(公告)号：EP1410151B1

公开(公告)日：2005-05-18

申请号：EP02760215.0

申请日：2002-07-02

Applicant: Infineon Technologies AG

Inventor： JANKE, Marcus ,  LAACKMANN, Peter

IPC: G06F1/00 ,  G07F7/10 ,  G06F9/318 ,  G06F11/16

CPC classification number: G06F21/75 ,  G06F9/30189 ,  G06F9/3885 ,  G06F11/1629 ,  G06F21/71 ,  G06F2201/845 ,  G06F2207/7219 ,  H04L9/003 ,  H04L9/12

Abstract: The invention relates to a processor comprising a first arithmetic-logic unit (2), a second arithmetic-logic unit (4) and a control device (6) for controlling both arithmetic-logic units (2, 4). The control device controls the arithmetic-logic units in such a manner that they operate, as desired, in a high-security operational mode, in which complementary data is processed, or in a parallel operational mode, in which independent data is processed, or in a security operational mode, in which the same the data is processed, or are located in a power saving mode, in which one of the arithmetic-logic units (2, 4) is switched off.

公开(公告)号：EP1090349B1

公开(公告)日：2002-02-20

申请号：EP99926160.5

申请日：1999-06-03

Applicant: SUN MICROSYSTEMS, INC.

Inventor： ROWLINSON, Stephen ,  OYELAKIN, Femi, A. ,  WILLIAMS, Emrys, J. ,  GARNETT, Paul, J.

IPC: G06F11/16 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F11/1658 ,  G06F11/1641 ,  G06F11/1683 ,  G06F13/4027 ,  G06F2201/845

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is configured to compare address and data phases of I/O accesses by the first and second processing sets. At least one dissimilar data register is provided for each processing set. The bridge control mechanism is operable in response to an address phase of a dissimilar data register write access to disregard any differences in the data phase for the dissimilar data write access. Non-deterministic data (for example relating to a real time clock) can be output from the processing sets in a combined (lockstep comparison) mode. A read destination address supplied in common by the first and second processing sets for a dissimilar data read access can cause data read from a determined one of the dissimilar data registers to be supplied the first and second processing sets. In this manner, the processing sets may have the dissimilar data replaced by the same data. The read destination address supplied in common by the first and second processing sets can determine the dissimilar data register from which data is read.

公开(公告)号：EP0752656A3

公开(公告)日：1999-08-11

申请号：EP96304199.1

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Horst, Robert W.

IPC: G06F11/16

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

公开(公告)号：EP0748079A3

公开(公告)日：1999-07-07

申请号：EP96304215.5

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Watson, William Joel ,  Baker, William Edward ,  Bruckert, William F. ,  Bunton, William Patterson

IPC: H04L12/26 ,  G06F11/00

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

公开(公告)号：EP0757315A2

公开(公告)日：1997-02-05

申请号：EP96304175.1

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Horst, Robert W. ,  Garcia, David J. ,  Bunton, William Patterson ,  Bruckert, William F. ,  Fowler, Daniel L. ,  Jones, Curtis Willard, Jr. ,  Sonnier, David Paul ,  Watson, William Joel ,  Williams, Frank A.

IPC: G06F11/16

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.
Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.
CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract translation: 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过路由设备互连，该路由设备也互连子处理器系统。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个存储器访问被拒绝。

公开(公告)号：EP0747833A2

公开(公告)日：1996-12-11

申请号：EP96304182.7

申请日：1996-06-06

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Horst, Robert W. ,  Garcia, David J.

IPC: G06F15/16 ,  G06F11/00

CPC classification number: G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.
Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.
CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract translation: 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过路由设备互连，该路由设备也互连子处理器系统。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个存储器访问被拒绝。

公开(公告)号：WO2015187218A1

公开(公告)日：2015-12-10

申请号：PCT/US2015/018169

申请日：2015-02-27

Applicant: PURE STORAGE, INC.

Inventor： HAYES, John ,  COLGROVE, John ,  LEE, Robert ,  VAJGEL, Peter ,  BOTES, Par

IPC: G06F12/02

CPC classification number: G06F11/1076 ,  G06F3/06 ,  G06F3/0607 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/067 ,  G06F3/0688 ,  G06F11/1068 ,  G06F11/108 ,  G06F11/1092 ,  G06F12/0246 ,  G06F2201/845 ,  G06F2212/7206 ,  G06F2212/7207 ,  H03M13/154

Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. The chassis includes power distribution, a high speed communication bus and the ability to install one or more storage nodes which may use the power distribution and communication bus. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

Abstract translation: 提供了单个机箱中的多个存储节点。 单个机箱中的多个存储节点被配置为一起作为存储集群通信。 多个存储节点中的每一个包括用于用户数据存储的非易失性固态存储器。 多个存储节点被配置为在整个多个存储节点中分配与用户数据相关联的用户数据和元数据，使得多个存储节点使用擦除编码保持读取用户数据的能力，尽管丢失了两个 的多个存储节点。 底盘包括配电，高速通信总线以及安装可能使用配电和通信总线的一个或多个存储节点的能力。 还提供了一种用于访问具有非易失性固态存储器的多个存储节点中的用户数据的方法。

公开(公告)号：WO2014084836A1

公开(公告)日：2014-06-05

申请号：PCT/US2012/067085

申请日：2012-11-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： KADRI, Rachid M

IPC: G06F11/20 ,  G06F1/00

CPC classification number: G06F11/2033 ,  G06F11/1064 ,  G06F11/2038 ,  G06F11/2043 ,  G06F11/2097 ,  G06F2201/845

Abstract: Examples disclose a multi-core circuit with a primary core associated with a primary portion of cache and a secondary core associated with a secondary portion of the cache. The secondary portion of the cache is redundant to the primary portion of the cache. Further, the examples of the multi-core circuit provide a control circuit to enable the secondary core for operation in response to a fault condition detected at the primary core, wherein the secondary portion of cache is enabled with the secondary core to resume an operation of the primary core.

Abstract translation: 示例公开了具有与高速缓存的主要部分相关联的主核心的多核电路和与高速缓存的次级部分相关联的次级核心。 缓存的次级部分对于高速缓存的主要部分是冗余的。 此外，多核电路的示例提供了控制电路，以使辅助核心能够响应于在主核心处检测到的故障状况而进行操作，其中高速缓存的次级部分能够被辅助核心恢复到 主要核心。