Control-type continuous ramp converting apparatus and conversion method

    公开(公告)号:GB9720979D0

    公开(公告)日:1997-12-03

    申请号:GB9720979

    申请日:1997-10-02

    Abstract: Control-type continuous ramp converting apparatus and method therefore. The present invention provides real-time processing of neurons in the neural network, easy implementation and reduction of manufacture cost of high density neurons in the neural network. The present invention comprises a first voltage controlling part for receiving a first voltage from an outside, and for non-linearly increasing a charged voltage in accordance with a differential continuous function of an exponential function; a second voltage controlling part for receiving a second voltage from an outside, and for non-linearly reducing a charged voltage in accordance with a differential continuous function of an exponential function; a charging part for charging an input current, and for providing the charged voltage of the charging part with the second voltage controlling part and an outside; and a plurality of switches for coupling outside and the first and the second voltage controlling part to the charging part, for selectively providing a third voltage from outside, an increased voltage and a decreased voltage based on the voltage of the charging part.

    Super self-aligned bipolar transistor with heterojunction

    公开(公告)号:DE19650493A1

    公开(公告)日:1997-06-26

    申请号:DE19650493

    申请日:1996-12-05

    Abstract: The transistor includes a semiconductor substrate, e.g. of silicon, with a buried collector and having an oxide film with a conductive, thin-film base electrode formed on the substrate one after another. The substrate is provided with a heterojunction of e.g. Si or SiGe Ge. The collector is surrounded by the conductive thin film and is formed in transistor active region, bounded by patterns of the conductive thin and first oxide films on the buried collector on both sides of the conductive thin film is formed a first spacing layer. A multilayer base is formed in the active region, while an emitter is grown selectively on the base in an emitter region, bounded by etching of a second oxide film, on whose both sides is formed a second spacing layer. The emitter carries an electrode, while a passivating insulation layer is formed on the structure surface. Metal coupling lines are formed on the base, emitter, and buried collector and go back through the insulation passivation layer and/or the two oxide layers.

    153.
    发明专利
    未知

    公开(公告)号:FR2742618A1

    公开(公告)日:1997-06-20

    申请号:FR9613973

    申请日:1996-11-15

    Abstract: An identification scheme, a digital signature scheme giving message recovery, and a digital signature scheme with appendix are disclosed. In processing and transmitting information, a transmitting counterpart of a transmission message is confirmed. The unauthorized modification of the message is confirmed and transmitting behavior is detected, thereby providing the reliable information service.

    154.
    发明专利
    未知

    公开(公告)号:FR2713365B1

    公开(公告)日:1997-05-23

    申请号:FR9414597

    申请日:1994-12-05

    Abstract: A modulo reduction method using a precomputed table to increase a reduction speed during the execution of ordinary operational processes using computers and comprises a first step which searches out with an index of an upper log2t (t>/=1) bit number and adds the value stored in a table to a lower n(n>/=512) bit number; a second step, which if the result, obtained from the addition of said lower n bit number to the number searched out from the table at said first step, produces an overflow (1 bit), eliminates said overflow and finishes the execution of an operation; and a third step, which if said overlow does not occur at said second step, adds N on a modulo N to the result obtained from said first step and finishes the execution of the operation.

    156.
    发明专利
    未知

    公开(公告)号:FR2738437A1

    公开(公告)日:1997-03-07

    申请号:FR9613643

    申请日:1996-11-08

    Abstract: An identification scheme which allows a prover to identify his own identity to a verifier more certainly and prevents already used authentication information from being re-used, a key exchange which uses a common secret key between two users in order not to allow an unauthorized to find it out, a digital signature scheme giving message recovery and digital signature scheme with appendix for producing a digital signature of a message recovery type or appendix type according to the size of a message to be signed, a multi-digital signature scheme for allowing multiple signers to generate digital signatures with respect to the same message and producing them in a message recovery type or appendix type according to the length of the message to be signed, and a blind digital signature scheme for producing a digital signature when a message to be signed should not be opened to the public as well as the signer and therefore a signer does not know the contents thereof.

    ID verification method esp. for computer data exchange

    公开(公告)号:FR2735307A1

    公开(公告)日:1996-12-13

    申请号:FR9606473

    申请日:1996-05-24

    Abstract: The method involves the authenticating partner choosing a number r and using three coefficients g, q and p to obtain a mathematical equation x. The equation number, together with the identity, I, is sent as authentication. A verifier signal (y) is generated by forming a mathematical function and using the value q. A secret key is then added to form the output verifier. The receiver investigates the values of the authentication and verification numbers. The secret key is then recovered and compared with the sender identity, to authenticate the information received.

    159.
    发明专利
    未知

    公开(公告)号:ES2040660B1

    公开(公告)日:1996-09-01

    申请号:ES9201485

    申请日:1992-07-16

    Inventor: IL SONG HAN

    Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.

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