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公开(公告)号：US20190286507A1
公开(公告)日：2019-09-19
申请号：US16356459
申请日：2019-03-18
Applicant: Melexis Technologies NV
Inventor： Heiko GRIMM
IPC: G06F11/07
Abstract: A method for detecting a failure in an electronic signal processing system having a signal processing path comprises a configurable functional unit for performing a given function and at least one redundant version of the signal processing path including a corresponding configurable functional unit for performing the given function and configuring a first operating point for the functional unit in the signal processing path for performing the given function and configuring a second operating point for the corresponding functional unit in the redundant version of the signal processing path. The second operating point is different from the first operating point. The method further comprises applying a same input signal to the functional unit and the corresponding functional unit, comparing a first output signal produced by the functional unit with a second output signal produced by the corresponding functional unit, and deriving a failure indication from the comparing.
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公开(公告)号：US10368423B2
公开(公告)日：2019-07-30
申请号：US16174411
申请日：2018-10-30
Applicant: Melexis Technologies NV
Inventor： Jorgen Sturm , Thomas Freitag , Raik Frost , Michael Bender
Abstract: A method of operating a plurality of driving units for powering electronic units comprises interchanging a data frame including a bit sequence, between a master control unit and at least one of a plurality of driving units at slave nodes. A step of applying an ID field comprises indicating the driving unit address using a first bit sub-string comprising N bits, allowing the master control unit to identify whether data should be received or transmitted, or allowing each addressed driving unit to decode which action is required by the master control unit, using an R/T command bit, performing a length decoding step, for including information in the ID field regarding the type of instructions included in the data frame, using an F function bit, and assigning data bits to different electronic units or indicating in the length of the bit string in the data field, using a second bit sub-string.
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公开(公告)号：US10326583B2
公开(公告)日：2019-06-18
申请号：US15981269
申请日：2018-05-16
Applicant: MELEXIS TECHNOLOGIES NV
Inventor： Jörgen Sturm , Thomas Freitag , Martin Bölter , Anton Babushkin
Abstract: A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.
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公开(公告)号：US20190132929A1
公开(公告)日：2019-05-02
申请号：US16174411
申请日：2018-10-30
Applicant: Melexis Technologies NV
Inventor： Jorgen STURM , Thomas FREITAG , Raik FROST , Michael BENDER
CPC classification number: H05B37/0254 , B60Q1/00 , B60R16/0238 , H04L67/12 , H04L2012/40273 , H05B33/0842
Abstract: A method of operating a plurality of driving units for powering electronic units comprises interchanging a data frame including a bit sequence, between a master control unit and at least one of a plurality of driving units at slave nodes. A step of applying an ID field comprises indicating the driving unit address using a first bit sub-string comprising N bits, allowing the master control unit to identify whether data should be received or transmitted, or allowing each addressed driving unit to decode which action is required by the master control unit, using an R/T command bit, performing a length decoding step, for including information in the ID field regarding the type of instructions included in the data frame, using an F function bit, and assigning data bits to different electronic units or indicating in the length of the bit string in the data field, using a second bit sub-string.
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公开(公告)号：US20190107604A1
公开(公告)日：2019-04-11
申请号：US16149256
申请日：2018-10-02
Applicant: Melexis Technologies NV
Inventor： Gaetan KOERS , Wouter LETEN , Sam MADDALENA , Ross KAY
Abstract: A sensor device (100) comprises an emitter device (106) arranged to emit electromagnetic radiation and having an emission region associated therewith. The sensor device (100) also comprises a detector device (108) arranged to receive electromagnetic radiation and having a detection region associated therewith, and an optical system (122). The emission region is spaced at a predetermined distance from the detection region. The optical system (122) defines a plurality of principal rays, a number of the plurality of principal rays intersecting the detection region. The number of the plurality of principal rays also intersect the emission region.
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Patent Agency Ranking
公开(公告)号：US20190043599A1
公开(公告)日：2019-02-07
申请号：US16048691
申请日：2018-07-30
Applicant: Melexis Technologies NV
Inventor： Darrell LIVEZEY
Abstract: The present invention relates to a sample-and-hold circuit comprising a plurality of sample-and-hold branches arranged in parallel and each comprising a buffer and a sample-and-hold block comprising one or more sample-and-hold cells characterised in that said sample-and-hold circuit further comprises a clock and timing circuit arranged for setting an adaptable time delay to enable sampling and sampling phase for each sample-and-hold block, wherein the time delay of at least one sample-and-hold block can be set to value bigger than one sampling clock period.
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公开(公告)号：US20180321065A1
公开(公告)日：2018-11-08
申请号：US15967809
申请日：2018-05-01
Applicant: Melexis Technologies NV
Inventor： Johan VERGAUWEN
CPC classification number: G01D18/00 , H03L7/0802 , H03L7/093 , H03L7/099 , H03M1/0604 , H03M1/1014 , H03M1/60
Abstract: An oscillator-based sensor interface circuit comprises at least two oscillators, at least one of which is arranged for receiving an electrical signal representative of an electrical quantity being a converted physical quantity, phase detection means arranged to compare output signals of the at least two oscillators and for outputting a digital phase detection output signal in accordance with the outcome of the comparing, a feedback element arranged for converting a representation of the digital phase detection output signal into a feedback signal used directly or indirectly to maintain a given relation between oscillator frequencies of the at least two oscillators, detection means for detecting a difference between the at least two oscillators; and at least one tuning element arranged for receiving the detected difference and for tuning at least one characteristic of the oscillator-based sensor interface circuit.
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公开(公告)号：US20180283956A1
公开(公告)日：2018-10-04
申请号：US15997836
申请日：2018-06-05
Applicant: Melexis Technologies NV
Inventor： Carl VAN BUGGENHOUT , Ben MAES , Karel VANROYE , Stijn REEKMANS
CPC classification number: G01J5/06 , G01J5/045 , G01J5/10 , G01J2005/0048 , G01J2005/065 , G01J2005/067 , G01J2005/106
Abstract: An infrared sensor assembly for sensing infrared radiation comprises infrared sensing elements and the infrared sensing compensation elements that are different so that, for a same flux on the infrared sensing elements and the infrared sensing compensation elements, the radiation responsive element of the infrared sensing elements absorbs more radiation than the radiation responsive element of the infrared sensing compensation elements, as to receive substantially more radiation than the radiation responsive element of the infrared sensing compensation elements. An output of the sensor array is a subtractive function of a sum of the signals of the plurality of infrared sensing elements and a sum of the signals of the plurality of the infrared sensing compensation elements such that at least linear and/or non-linear parasitic thermal fluxes are at least partly compensated for.
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公开(公告)号：US20180218984A1
公开(公告)日：2018-08-02
申请号：US15882073
申请日：2018-01-29
Applicant: MELEXIS TECHNOLOGIES NV
Inventor： Appolonius Jacobus VAN DER WIEL
IPC: H01L23/552 , H01L29/84 , H01L29/45 , H01L29/06 , H01L23/522 , H01L23/532 , H01L23/00 , H01L21/768
Abstract: A sensor device for use in harsh media, comprising a silicon die comprises a lowly doped region, and a contact layer, contacting the silicon die. The contact layer comprises a refractory metal and an ohmic contact to the silicon die via a silicide of the refractory metal. A noble metal layer is provided over the contact layer such that the contact layer is completely covered by the noble metal layer. The noble metal layer comprises palladium, platinum or a metal alloy of palladium and/or platinum. The noble metal layer is patterned to form an interconnect structure and a contact connecting via the contact layer to the ohmic contact. The noble metal layer is adapted for providing a shield to prevent modulation of the lowly doped region by surface charges. The noble metal layer may advantageously protect the contact layer against harsh media in an external environment of the sensor device.
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公开(公告)号：US20180203059A1
公开(公告)日：2018-07-19
申请号：US15873325
申请日：2018-01-17
Applicant: Melexis Technologies NV
Inventor： Vincenzo SACCO , Mathieu POEZART
IPC: G01R31/26 , G01D3/08 , G06F11/16 , G01R31/28 , G01R31/3187
CPC classification number: G01R31/2644 , G01D3/08 , G01D5/24466 , G01R31/2829 , G01R31/2856 , G01R31/2884 , G01R31/3187 , G05B9/03 , G06F11/1633
Abstract: A sensor system for providing a main signal and an error signal, comprising: a sensor unit providing a sensor signal; a first signal processor downstream of the sensor unit, adapted for receiving a second signal equal to or derived from a sensor signal, and for performing a first operations on the second signal so as to provide a first processed signal; a second signal processor for receiving the first processed signal and for performing second operations inverse of the first operations, so as to provide a second processed signal; and an evaluation unit for receiving the second signal and the second processed signal, and for evaluating whether the second signal matches the second processed signal within a predefined tolerance margin, and for providing the error signal.
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