公开(公告)号：EP1653747A2

公开(公告)日：2006-05-03

申请号：EP05022773.5

申请日：2005-10-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kaushik, Saha ,  Chakraborty, Chiranjib ,  Chatterjee, Subrata

IPC: H04N7/62

CPC classification number: H04N21/4305

Abstract: A system for clock recovery in digital video communication comprising a delay measurement block for generating PCR input signals and for continuously determining time interval between successive PCR input signals, a first storage device for generating a first PCR signal corresponding to said time interval between arrival of successive PCR input signals, a PCR inter-arrival time computation filtering device for determining the average time of arrival difference between successive PCR packets. An error correction device for minimizing the error in the average PCR difference between successive PCR packets, a controlled system clock generator connected to the output of said error correction device to generate system clock, a second storage device for generating a first system clock output, a controlled clock period difference computation element for computing the clock period difference between said first and second system clock output, and said controlled clock period difference computation element is coupled at its output to said error correction device to form a feedback circuit for minimizing the error between said system clock output and successive PCR differences observed.

Abstract translation: 一种用于数字视频通信中的时钟恢复的系统，包括用于产生PCR输入信号的延迟测量块和用于连续地确定连续的PCR输入信号之间的时间间隔的第一存储装置，用于产生对应于连续到达之间的所述时间间隔的第一PCR信号 PCR输入信号，PCR到达间时间计算滤波装置，用于确定连续PCR分组之间的平均到达时差。 一种用于最小化连续PCR分组之间的平均PCR差异误差的纠错装置，连接到所述纠错装置的输出以产生系统时钟的受控系统时钟发生器，用于产生第一系统时钟输出的第二存储装置， 控制时钟周期差计算元件，用于计算所述第一和第二系统时钟输出之间的时钟周期差，并且所述受控时钟周期差计算元件在其输出处耦合到所述纠错装置，以形成反馈电路，以使所述第一和第二系统时钟输出之间的误差最小化 观察系统时钟输出和连续的PCR差异。

公开(公告)号：EP1653618A2

公开(公告)日：2006-05-03

申请号：EP05110094.9

申请日：2005-10-27

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Agarwal, Nitin

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A PWM generator system providing improved duty cycle resolution comprising a sub-cycle generator for generating a sub-cycle with a period that is a small fraction of the maximum PWM period to be generated. An integral sub-cycle estimator is coupled to said sub-cycle generator for determining the integral number of said sub-cycles for on and off time of said PWM waveform, and an additional sub-cycle estimator for determining the additional fractional sub-cycle required to provide said on and off time. A timer is coupled to said integral sub cycle estimator and said additional sub cycle estimator for controlling PWM output switching for the on and off time of the integral and additional fractional sub cycles.

Abstract translation: 一种提供改善的占空比分辨率的PWM发生器系统，包括用于产生具有要产生的最大PWM周期的一小部分的周期的子周期的子周期发生器。 积分子周期估计器耦合到所述子周期发生器，用于确定所述PWM波形的导通和截止时间的所述子周期的整数，以及用于确定所需的额外分数子周期的附加子周期估计器 提供说明开关时间。 定时器耦合到所述积分子周期估计器和所述附加子周期估计器，用于控制用于积分和附加分数子周期的开和关时间的PWM输出切换。

公开(公告)号：EP1650869A1

公开(公告)日：2006-04-26

申请号：EP05109736.8

申请日：2005-10-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Bhuvanagiri, Aditya ,  Malik, Rakesh ,  Chawla, Nitin

IPC: H03H17/02 ,  G06F7/00 ,  G06F17/50

CPC classification number: H03H17/0225

Abstract: The present invention provides a device for implementing a sum-of-products expression comprising a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/ complex sum-of -products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from said 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein , a third set of 2SAD blocks receiving recursively and vertically optimized response from said first set of 2SAD block and said second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from said blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from said fourth set of 2SAD blocks, for generating the final output.

Abstract translation: 本发明提供了一种用于实现产品总和表达式的装置，包括：第一组2-输入移位和加法（2SAD）块，其接收用于产生第一组的第一组的系数组/复数和和积表达式 通过在其中应用递归优化来实现部分优化的表达项;第二组1-输入移位和加法（1SAD）块，其从所述2SAD块接收响应，用于通过在其中应用垂直优化来产生第二组部分优化表达项，第三组 一组2SAD块从所述第一组2SAD块和所述第二组1SAD块接收递归和垂直优化的响应，用于通过在其中应用水平优化来产生第三组部分优化的表达项，第四组2SAD块从所述 用于通过应用分解和因式分解来产生第四组部分优化的表达式的块，以及第五组2SAD块 接收来自所述第四组2SAD块的响应，用于产生最终输出。

公开(公告)号：EP1585024A1

公开(公告)日：2005-10-12

申请号：EP05102697.9

申请日：2005-04-06

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Bahl, Swapnil ,  Singh, Balwant

IPC: G06F5/06 ,  G11C7/10

CPC classification number: G06F5/10 ,  G11C7/1006

Abstract: An improved on-chip storage memory for storing variable data bits comprising an on-chip storage memory system for storing variable data bits comprising a memory for storing data bits; a wrapper for converting said memory into a first-in first-out (FIFO) memory; and a controller for performing operations on said memory.

Abstract translation: 一种用于存储可变数据位的改进的片上存储存储器，包括片上存储存储器系统，用于存储包括用于存储数据位的存储器的可变数据位; 用于将所述存储器转换成先进先出（FIFO）存储器的包装器; 以及用于对所述存储器执行操作的控制器。

公开(公告)号：EP1271782B1

公开(公告)日：2005-05-18

申请号：EP02012610.8

申请日：2002-06-06

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Singh, Moninder ,  Chaudhry, Anurag

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17736

公开(公告)号：EP1492234A2

公开(公告)日：2004-12-29

申请号：EP04014644.1

申请日：2004-06-22

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Roy, Amit

IPC: H03K17/22

CPC classification number: H03K17/223 ,  H03K2217/0036

Abstract: The present invention provides an improved Power-On-reset (POR) circuit providing enhanced reliability and automatic power-down capability, comprising a supply voltage sensing circuit (IS1,P1,VCCS), a delay element (1) connected to the output of the supply voltage sensing circuit, and a switch (P2,N2) that activates the output POR signal when the output of the delay element indicates a reduced supply voltage and deactivates the POR output and provides feedback to reduce current through the supply voltage sensing circuit once the supply voltage is normal.

Abstract translation: 电路具有电源电压检测电路和连接到感测电路的输出的电容器（C1）。 当电容器的输出指示电压降低时，开关激活输出上电复位（POR）信号。 当电源电压正常时，开关关闭POR输出并提供反馈以减少通过感测电路的电流。

公开(公告)号：EP1363132A3

公开(公告)日：2004-02-04

申请号：EP03010587.8

申请日：2003-05-12

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Pathak, Shalini ,  Swami, Parvesh

IPC: G01R31/3185 ,  G11C29/00 ,  G06F11/10

CPC classification number: G11C29/025 ,  G01R31/318516 ,  G11C29/02 ,  G11C29/12

Abstract: A Programmable Logic Device (PLD) incorporating the ability to test the configuration memory either independently or during configuration, comprising a selector for selecting a particular column or row of the configuration memory array, an input data store for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row, an output data store for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.

公开(公告)号：EP1363132A2

公开(公告)日：2003-11-19

申请号：EP03010587.8

申请日：2003-05-12

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Pathak, Shalini ,  Swami, Parvesh

IPC: G01R31/3185

CPC classification number: G11C29/025 ,  G01R31/318516 ,  G11C29/02 ,  G11C29/12

Abstract: A Programmable Logic Device (PLD) incorporating the ability to test the configuration memory either independently or during configuration, comprising a selector for selecting a particular column or row of the configuration memory array, an input data store for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row, an output data store for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.

Abstract translation: 一种可编程逻辑器件（PLD）包含以测试配置存储器要么unabhängig或配置过程中，在输入数据存储单元选择配置存储器阵列的特定列或行用于存储需要被存储在配置数据，其包括选择器的能力 用于测试所选择的行或列来输出数据存储用于从所选的列或行，和测试逻辑存储输出没选择的列或行，或测试数据提供控制信号用于验证正确的操作的数据线的 配置存储器阵列，而不会干扰存储在存储器阵列中的数据。

公开(公告)号：EP1324619A3

公开(公告)日：2003-08-13

申请号：EP02022752.6

申请日：2002-10-11

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana, Flat No. 7

IPC: H04N7/62 ,  H04N7/56 ,  H03L7/197 ,  H04N5/12 ,  H03L7/00

CPC classification number: H04N21/4305 ,  H03L7/0992 ,  H03L7/181

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values (2.9) characterized in that controlled clock source means consists of controllable digital Fractional Divider means (2.5) receiving a control value from digital comparator means (2.3) and a clock input from a digital clock synthesizer means (2.8) driven by a fixed oscillator means (2.7).

Abstract translation: 一种用于从包含嵌入式基准时钟值的数据流进行时钟恢复的方法和改进装置，控制时钟源包括从数字比较器接收控制值的可控数字分数分频器和由固定振荡器驱动的数字时钟合成器输入的时钟。

公开(公告)号：EP1298320A2

公开(公告)日：2003-04-02

申请号：EP02021534.9

申请日：2002-09-26

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Dutt, Saibal ,  Dasgupta, Nabarun ,  Kulshrestha, Nikhil

IPC: F02P3/08

CPC classification number: F02P15/10 ,  F02D2041/2075 ,  F02P3/0846 ,  F02P3/0884

Abstract: This invention relates to an improved Capacitor Discharge Ignition (CDI) system capable of generating intense continuous electrical discharge at spark gap for any desired duration, characterized in that it includes a second controllable power switching means with its input terminal connected to the output terminal of said high voltage d.c. source means, its output terminal connected to the input terminal of said first power switching means, and its control terminal connected to a second output of said control means, the arrangement being such that said first controllable power switching means is used for discharging said discharge capacitor and said second controllable power switching means causes charging of said discharge capacitor, thereby enabling an ignition current through said ignition coil for any desired number of cycles during both the charge and discharge cycles of said discharge capacitor.

Abstract translation: 本发明涉及一种改进的电容放电点火（CDI）系统，其能够在火花隙处产生强烈的连续放电，持续任何期望，其特征在于，其包括第二可控功率开关装置，其输入端连接到所述 高压直流 源装置，其输出端连接到所述第一功率开关装置的输入端，其控制端连接到所述控制装置的第二输出端，该装置使得所述第一可控功率开关装置用于对所述放电电容器 并且所述第二可控功率开关装置使所述放电电容器充电，从而使得在所述放电电容器的充电和放电循环期间能够通过所述点火线圈的点火电流达到任何所需数量的周期。