公开(公告)号：US20110012266A1

公开(公告)日：2011-01-20

申请号：US12832177

申请日：2010-07-08

Applicant: Michio HORIUCHI ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

Inventor： Michio HORIUCHI ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC: H01L23/538 ,  H01L21/50

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

Abstract translation: 在半导体器件中，衬底包括从衬底的顶表面到底表面穿透衬底的多个线导体。 半导体芯片固定在基板的孔中。 在衬底和半导体芯片的顶表面上形成第一绝缘层。 第一布线层形成在第一绝缘层上，并且经由第一绝缘层的通孔与半导体芯片电连接，一些线导体暴露于一个通孔。 在基板和半导体芯片的底面上形成第二绝缘层。 第二布线层形成在第二绝缘层上，并且经由第二绝缘层的通孔与暴露于通孔的一些线导体电连接。

公开(公告)号：US20100307808A1

公开(公告)日：2010-12-09

申请号：US12792334

申请日：2010-06-02

Applicant: Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Masao NAKAZAWA

Inventor： Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Masao NAKAZAWA

IPC: H05K1/11

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K1/0287 ,  H05K1/0306 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/09609 ,  H05K2201/09945 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wiring board includes a core substrate having a structure including an insulating base material and a large number of filamentous conductors densely provided in the insulating base material and piercing the insulating base material in a thickness direction thereof. Pads made of portions of wiring layers are oppositely disposed on both surfaces of the core substrate and electrically connected to opposite ends of a plurality of filamentous conductors in such a manner that the pads share the filamentous conductors. A wiring connection between one surface side and the other surface side of the core substrate is made through the pads. The insulating base material is made of an inorganic dielectric. Pads made of portions of the wiring layers are disposed on both surfaces of the core substrate and electrically connected only to corresponding one end sides of different groups each formed of a plurality of filamentous conductors.

Abstract translation: 布线基板包括芯基板，该芯基板具有密封地设置在绝缘基材中的绝缘基材和大量丝状导体，并且在其厚度方向上刺穿绝缘基材。 由布线层部分构成的垫相对地设置在芯基板的两个表面上，并且以多个丝状导体的相对端电连接，使得焊盘共享丝状导体。 通过焊盘制造芯基板的一个表面侧和另一个表面侧之间的布线连接。 绝缘基材由无机电介质制成。 由布线层的一部分制成的垫片设置在芯基板的两个表面上，并且仅电连接到由多个丝状导体形成的不同组的相应一端侧。

公开(公告)号：US07694869B2

公开(公告)日：2010-04-13

申请号：US11409242

申请日：2006-04-21

Applicant: Steven A. Cordes ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

Inventor： Steven A. Cordes ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

IPC: B23K31/00 ,  H05K3/34

CPC classification number: B23K3/0638 ,  B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3478 ,  H05K3/3484 ,  H05K2201/09945 ,  H05K2203/0113 ,  H05K2203/043 ,  H01L2924/00

Abstract: A system, method, and device for applying conductive bonding material to a substrate are disclosed. The method includes providing conductive bonding material in a plurality of cavities of a mold. A total number of cavities in the plurality of cavities being greater than a total number of at least one conductive pad of a circuit supporting substrate corresponding to the mold. The conductive bonding material in the mold is heated to a reflow temperature of the conductive bonding material. At least one wettable surface is placed in substantial contact with the heated conductive bonding material in at least one cavity. The mold and the corresponding circuit supporting substrate are brought in close proximity to each other such that the heated conductive bonding material in at least one cavity comes in contact with at least one conductive pad of the corresponding circuit supporting substrate.

Abstract translation: 公开了一种用于将导电接合材料施加到基底的系统，方法和装置。 该方法包括在模具的多个空腔中提供导电接合材料。 多个空腔中的空腔的总数大于对应于模具的电路支撑衬底的至少一个导电焊盘的总数。 将模具中的导电接合材料加热至导电接合材料的回流温度。 在至少一个空腔中至少一个可润湿表面被放置成与被加热的导电接合材料基本接触。 模具和相应的电路支撑衬底彼此靠近，使得至少一个空腔中的加热的导电接合材料与相应的电路支撑衬底的至少一个导电焊盘接触。

公开(公告)号：US20040178000A1

公开(公告)日：2004-09-16

申请号：US10655845

申请日：2003-09-04

Inventor： Tzyy-Jang Tseng

IPC: H05K001/11

CPC classification number: H05K3/4602 ,  H05K1/0287 ,  H05K1/0298 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/09609 ,  H05K2201/09945

Abstract: A standardized or partial standardized circuit board core comprises at least a dielectric core layer and a plurality of conductive posts, in which the dielectric layer has a first surface and a related second surface. The conductive posts pass through the dielectric core layer and connect to the first and second surfaces of the dielectric layer respectively. The conductive posts are array arranged or arranged in a constant distance form in the dielectric core layer. Moreover, the standardized or partial standardized circuit board core further includes two conductive layers, which are covered on the first and second surfaces of the dielectric core layer.

Abstract translation: 标准化或部分标准化电路板芯包括至少介电芯层和多个导电柱，其中介电层具有第一表面和相关的第二表面。 导电柱穿过介质芯层并分别连接到电介质层的第一和第二表面。 导电柱在介质芯层中以恒定距离的形式排列或布置。 此外，标准化或部分标准化电路板芯还包括两个导电层，其被覆在介质芯层的第一和第二表面上。

公开(公告)号：US06774486B2

公开(公告)日：2004-08-10

申请号：US09974947

申请日：2001-10-10

Applicant: Larry D. Kinsman

Inventor： Larry D. Kinsman

IPC: H01L2348

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09945 ,  H01L2924/00

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.

公开(公告)号：US20030052155A1

公开(公告)日：2003-03-20

申请号：US10062515

申请日：2002-02-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Raj N. Master ,  Cheon-Seng Chan ,  Ooi-Tong Ong

IPC: B23K031/02

CPC classification number: H05K3/3478 ,  H05K2201/09945 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/082

Abstract: A universal attach manufacturing process employs a boat onto which solder balls or columns are loaded. A universal attach line has a number of attach station to accommodate different types of attach processes. Depending on the process and the desired configuration and form factor of the array of solder balls or columns, a template is selected that covers some of the holes in the universal boat, and exposes other holes. The solder balls or columns are held securely in the exposed holes, and a substrate is placed onto the solder balls. Once loaded with balls or columns, the universal boat is transported to only the appropriate attach stations in the universal attach line, where the different attach operations for a given attach process, such as high temperature ball attach, eutectic ball attach, or column attach, are performed.

Abstract translation: 通用连接制造工艺采用装载有焊球或列的船。 通用连接线具有多个连接台以适应不同类型的连接过程。 根据工艺以及焊球或列阵列的期望配置和形状因素，选择覆盖通用船中的一些孔的模板，并露出其他孔。 焊球或支柱牢固地固定在暴露的孔中，并且将衬底放置在焊球上。 一旦装载了球或柱，通用船仅被运送到通用附着线中的适当的附接站，其中对于给定的附接过程（例如高温球附着，共晶球附着或柱附着）的不同附着操作， 被执行。

公开(公告)号：US06329631B1

公开(公告)日：2001-12-11

申请号：US09390638

申请日：1999-09-07

Applicant: Ray Yueh

Inventor： Ray Yueh

IPC: B23K2620

CPC classification number: H05K3/3484 ,  B23K3/06 ,  B23K35/0222 ,  B23K35/025 ,  B23K2101/40 ,  H05K3/3478 ,  H05K2201/09945 ,  H05K2201/10424 ,  H05K2203/0338 ,  H05K2203/107

Abstract: A transparent plastic solder strip being provided with a plurality of solder holes for each accommodating an amount of solder paste therein. These solder holes have a very small diameter and are uniformly and densely distributed throughout the solder strip in a specific pattern, such that a proper density of the solder hole on the solder strip is obtained to always allow sufficient number of solder holes to be covered in an applied area for sufficient amount of solder paste to be melted by laser beams and transferred from the solder strip to islands on a BGA carrier for bonding the carrier to a semiconductor device. It is no longer necessary to register the solder holes with the islands on the carrier to complete the solder transfer.

Abstract translation: 一个透明的塑料焊料条被提供有多个焊接孔，用于每个焊料孔容纳一定数量的焊膏。 这些焊接孔具有非常小的直径，并且以特定图案均匀且密集地分布在整个焊料条中，使得获得焊料条上的焊料孔的适当密度，以便始终允许足够数量的焊料孔被覆盖 用于通过激光束熔化足够量的焊膏并将其从焊料条转移到BGA载体上的岛以将载体接合到半导体器件的施加区域。 不再需要在载体上的岛上注册焊锡孔，以完成焊料传输。

公开(公告)号：US20010008169A1

公开(公告)日：2001-07-19

申请号：US09108158

申请日：1998-06-30

Applicant: 3M INNOVATIVE PROPERTIES COMPANY

Inventor： GLEN CONNELL ,  BERRY S. CARPENTER ,  PETER B. HOGERTON ,  HIROAKI H. YAMAGUCHI

IPC: B32B003/30 ,  B32B009/00 ,  B32B001/00

CPC classification number: H05K3/323 ,  C09J9/02 ,  H05K2201/09945 ,  H05K2201/10234 ,  H05K2203/0113 ,  H05K2203/0338 ,  Y10T156/109 ,  Y10T156/1093 ,  Y10T428/14 ,  Y10T428/24372 ,  Y10T428/24413 ,  Y10T428/24669 ,  Y10T428/24678

Abstract: Disclosed is an anisotropic conductive adhesive having an adhesive layer and conductive particles individually adhered to the adhesive layer, the conductive particles being arranged in an ordered array. The size of the conductive particles is at least somewhat smaller than the thickness of the adhesive layer. Also disclosed is an anisotropic conductive adhesive having an adhesive layer, conductive particles individually adhered to the adhesive layer, and a release liner having an ordered array of dimples. The conductive particles reside in a single layer in the dimples. The anisotropic conductive adhesive is made by placing the conductive particles in an ordered array of dimples on a low adhesion surface. An adhesive layer is then laminated on top such that the conductive particles individually adhere to the adhesive layer. The anisotropic conductive adhesive may be used to electrically connect fine pitch electrodes on opposing circuit layers.

Abstract translation: 公开了一种各向异性导电粘合剂，其具有粘合剂层和导电颗粒单独地粘附到粘合剂层，导电颗粒以有序阵列布置。 导电颗粒的尺寸至少略小于粘合剂层的厚度。 还公开了具有粘合剂层的各向异性导电粘合剂，单独粘附到粘合剂层的导电颗粒和具有有序排列的凹坑的剥离衬垫。 导电粒子位于凹坑中的单层中。 各向异性导电粘合剂通过将导电颗粒放置在低粘附表面上的有序排列的凹坑中而制成。 然后将粘合剂层层压在顶部上，使得导电颗粒单独地粘附到粘合剂层。 各向异性导电粘合剂可用于将相对电路层上的细间距电极电连接。

公开(公告)号：US5910755A

公开(公告)日：1999-06-08

申请号：US959711

申请日：1997-10-28

Applicant: Hidehiro Mishiro ,  Kenichiro Tsubone ,  Mitsunori Abe ,  Rie Takada

Inventor： Hidehiro Mishiro ,  Kenichiro Tsubone ,  Mitsunori Abe ,  Rie Takada

IPC: H03H7/01 ,  H05K1/00 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H03H7/075 ,  H01G4/255

CPC classification number: H05K1/162 ,  H03H7/0115 ,  H03H7/175 ,  H05K1/0287 ,  H05K1/029 ,  H03H2001/0085 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K2201/09309 ,  H05K2201/09945

Abstract: A laminate capacitor circuit board which permits constants of various kinds of circuit elements to be set by selectively effected connections between wiring layers, and a laminate capacitor circuit board which permits distributed circuit constants in a high-frequency wiring layer sandwiched between two shielding wiring layers to be set as desired. These circuits are formed with at least a pattern of a conductive foil on each dielectric layer, and include a plurality of wiring layers laminated one upon another, a wiring layer for connections laminated to a surface of the plurality of wiring layers laminated one upon another, a plurality of terminal patterns formed on the wiring layer for connections in a state insulated from each other, a plurality of vias for electrically connecting at least two of the plurality of terminal patterns to corresponding ones of the plurality of wiring layers, and connecting means for selectively connecting the plurality of terminal patterns to each other.

Abstract translation: 通过选择性地实现布线层之间的连接来设置允许各种电路元件的常数的叠层电容器电路板，以及层叠电容器电路板，其允许夹在两个屏蔽布线层之间的高频布线层中的分布电路常数 根据需要设定。 这些电路在每个电介质层上至少形成有导电箔的图案，并且包括彼此层叠的多个布线层，层叠到彼此层叠的多个布线层的表面的用于连接的布线层， 形成在布线层上的多个端子图案，用于在彼此绝缘的状态下连接;多个通孔，用于将多个端子图案中的至少两个电连接到多个布线层中的相应端子;以及连接装置， 选择性地将多个端子图案彼此连接。

公开(公告)号：US5618189A

公开(公告)日：1997-04-08

申请号：US588193

申请日：1996-01-18

Applicant: Sungho Jin ,  Mark T. McCormack

Inventor： Sungho Jin ,  Mark T. McCormack

IPC: B23K35/02 ,  B23K35/14 ,  H05K3/34 ,  H05K3/36 ,  H01R9/09

CPC classification number: B23K35/0222 ,  H05K3/3436 ,  B23K35/0227 ,  B23K35/0244 ,  H01L2924/0002 ,  H05K2201/0215 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2203/0235 ,  H05K2203/0769 ,  H05K2203/104 ,  Y02P70/613

Abstract: Electronic devices having at least two components with mating contact pads are provided with high-aspect-ratio solder joints between the mating pads. These joints ar formed by placing a composite solder medium containing solder wires in an electrically insulating matrix such that at least two solder wires are in contact with the mating pads, and fusing the wires to the pads. The insulating matrix with remainder of solder wires is then optionally removed from between the said at least two components. The composite solder medium is formed by preparing an elongated body of solder wires in an insulating matrix and cutting off slices of the composite solder medium, the solder wires having a high-aspect-ratio of length to their diameter. Alternatively sheets of the composite solder medium are prepared by magnetically aligning solder coated magnetic particles into columns arranged transverse of an insulating matrix and heating sufficiently to fuse the solder in each column into a continuously conducting solder path.

Abstract translation: 具有至少两个具有配合接触垫的部件的电子设备在配合焊盘之间设置有高纵横比焊接点。 这些接头通过将包含焊丝的复合焊料介质放置在电绝缘基体中而形成，使得至少两个焊丝与配合焊盘接触，并将焊丝熔合到焊盘。 然后可选地从所述至少两个部件之间移除具有剩余焊丝的绝缘基体。 复合焊料介质通过在绝缘基体中制备细长的焊丝体并且切断复合焊料介质的切片而形成，该焊丝具有与其直径的长宽比的高纵横比。 或者，复合焊料介质的片材通过将焊接涂覆的磁性颗粒磁化地排列成横向于绝缘矩阵布置的列并充分加热以将每个列中的焊料熔合成连续导电的焊接路径来制备。