公开(公告)号：US20040171225A1

公开(公告)日：2004-09-02

申请号：US10795377

申请日：2004-03-09

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Motoshige Igarashi

IPC: H01L021/8238 ,  H01L021/336 ,  H01L021/3205 ,  H01L021/4763

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/6653

Abstract: A gate insulating film is formed on a semiconductor substrate, and a gate electrode is formed by deposition of semiconductor material on the gate insulating film. An amorphous layer is then formed along the surface of or inside the gate electrode, and side walls are formed on the gate electrode. Finally, impurities are implanted into the semiconductor substrate by ion implantation while the gate electrode and the side walls are used as masks.

Abstract translation: 在半导体衬底上形成栅极绝缘膜，并且通过在栅极绝缘膜上沉积半导体材料形成栅电极。 然后沿着栅电极的表面或内部形成非晶层，并且在栅电极上形成侧壁。 最后，通过离子注入将杂质注入到半导体衬底中，同时将栅电极和侧壁用作掩模。

公开(公告)号：US20040170387A1

公开(公告)日：2004-09-02

申请号：US10677228

申请日：2003-10-03

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Yoshinori Matsuura ,  Hiroshi Segawa

IPC: H04N005/76

CPC classification number: H04N21/2368 ,  H04N21/23406 ,  H04N21/234318 ,  H04N21/4341 ,  H04N21/44004

Abstract: A time zone start time point calculating unit calculates a time zone to be set in a VOBU in accordance with audio bit rate. A time zone comparing unit compares a time point at which an audio pack is to be multiplexed with the time zone calculated by the time zone start time point calculating unit. A flag setting unit sets whether the audio pack is to be completed or not in accordance with the result of comparison by the time zone comparing unit. Therefore, a completing process takes place before a VOBU boundary, and a completed PCK will not be generated immediately after the VOBU boundary. Thus, generation of a buffer overflow can be prevented.

Abstract translation: 时区开始时刻计算单元根据音频比特率计算要设置在VOBU中的时区。 时区比较单元将音频包与多路复用的时间点与由时区开始时间点计算单元计算的时区进行比较。 标志设置单元根据时区比较单元的比较结果来设置是否要完成音频包。 因此，在VOBU边界之前进行完成处理，并且在VOBU边界之后不会立即生成完成的PCK。 因此，可以防止产生缓冲器溢出。

公开(公告)号：US20040169228A1

公开(公告)日：2004-09-02

申请号：US10619431

申请日：2003-07-16

Applicant: Renesas Technology Corp.

Inventor： Motoi Ashida ,  Takashi Terada

IPC: H01L027/01

CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with a CMOS transistor structure in which a gate electrode and a wire connecting an Nnull-type active region and a Pnull-type active region overlap each other in plan view, to reduce a footprint of the CMOS transistor structure, is provided. An Nnull-type active region (1) of an n-channel MOS transistor and a Pnull-type active region (2) of a p-channel MOS transistor are formed in a surface portion of a semiconductor substrate by ion implantation or the like. Gate electrodes (3) are formed on the Nnull-type active region (1) and the Pnull-type active region (2). Insulating films (4, 5) of silicon nitride are formed on the gate electrodes (3). An interlayer insulating film (6) of silicon oxide is formed over the gate electrodes (3) covered with the insulating films (4, 5), by CVD or the like. Openings (7) for accommodating wires connecting the Nnull-type active region (1) and the Pnull-type active region (2) are formed in the interlayer insulating film (6). A metal film such as an aluminum film is buried in the openings (7), to form buried wires (8).

Abstract translation: 具有CMOS晶体管结构的半导体器件，其中栅极电极和连接N +型有源区和P +型有源区的导线在平面图中彼此重叠，以减少CMOS的占空比 晶体管结构。 在沟道MOS晶体管的n沟道MOS晶体管和P +型有源区（2）中的N +型有源区（1）形成在半导体衬底的表面部分 离子注入等。 栅电极（3）形成在N +型有源区（1）和P +型有源区（2）上。 在栅电极（3）上形成氮化硅绝缘膜（4,5）。 通过CVD等在绝缘膜（4,5）覆盖的栅电极（3）上形成氧化硅层间绝缘膜（6）。 用于容纳连接N +型有源区（1）和P +型有源区（2）的导线的开口（7）形成在层间绝缘膜（6）中。 将诸如铝膜的金属膜掩埋在开口（7）中，以形成掩埋线（8）。

公开(公告)号：US20040168127A1

公开(公告)日：2004-08-26

申请号：US10667354

申请日：2003-09-23

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Tomohiro Sakurai ,  Toru Kengaku ,  Tatsuya Ueda

IPC: G06F017/21

CPC classification number: G06T1/60 ,  G06T3/40

Abstract: When a line number counted by a line number counting unit corresponds to a prescribed line number, a transfer source address generating unit adds an offset address set in an offset address setting unit to respective transfer source addresses to output as addresses to a memory. A DMA control unit controls DMA transfer in accordance with a transfer source address generated by the transfer source address generating unit and a transfer destination address generated by a transfer destination address generating unit. Thus, rapid enlargement/reduction of image data becomes possible.

Abstract translation: 当由行数计数单元计数的行号对应于规定行号时，传送源地址产生单元将偏移地址设置单元中设置的偏移地址添加到各个传送源地址，作为地址输出到存储器。 DMA控制单元根据由传送源地址生成单元生成的传送源地址和由传送目的地地址生成单元生成的传送目的地地址进行DMA传送。 因此，图像数据的快速放大/缩小成为可能。

公开(公告)号：US20040167755A1

公开(公告)日：2004-08-26

申请号：US10630775

申请日：2003-07-31

Applicant: Renesas Technology Corp.

Inventor： Kazuya Kamon

IPC: G06F017/10

CPC classification number: B24B37/042 ,  G06F17/5022 ,  G06F2217/12 ,  H01L21/67253 ,  Y02P90/265

Abstract: A simulator is provided which can simulate in consideration of various parameters in a CMP process. A pattern density two-dimensional distribution calculating part takes a pattern density two-dimensional distribution image. A mesh adjusting part performs a mesh adjustment of a measured data. A height distribution calculating part calculates a height distribution based on the pattern density two-dimensional distribution image. A correlation coefficient calculating part calculates a correlation coefficient by performing a least squares analysis of a measured data and a height distribution data. Passing through a Fourier calculation part, spatial filter part, and reverse Fourier calculating part, the pattern density two-dimensional distribution image becomes a pattern density two-dimensional distribution image. This distribution image further passes through a height distribution calculating part, resulting in a height distribution data. The correlation coefficient calculating part calculates a correlation coefficient by performing a least squares analysis of the height distribution data and measured data after CMP process.

Abstract translation: 提供了可以在CMP过程中考虑各种参数来模拟的模拟器。 图案密度二维分布计算部分采用图案密度二维分布图像。 网格调整部分执行测量数据的网格调整。 高度分布计算部分基于图案密度二维分布图像来计算高度分布。 相关系数计算部分通过对测量数据和高度分布数据进行最小平方分析来计算相关系数。 通过傅里叶计算部分，空间滤波器部分和反傅立叶计算部分，图案密度二维分布图像变为图案密度二维分布图像。 该分布图像进一步通过高度分布计算部，得到高度分布数据。 相关系数计算部通过对CMP处理后的高度分布数据和测量数据进行最小二乘法分析来计算相关系数。

公开(公告)号：US20040165452A1

公开(公告)日：2004-08-26

申请号：US10689062

申请日：2003-10-21

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Masaya Nakano

IPC: G11C007/00

CPC classification number: G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/401 ,  G11C29/14 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50016

Abstract: An internal RAS generating circuit generates an internal signal instructing activation of a word line, based on a control command received from the outside. The internal RAS generating circuit activates the internal signal at least during a period in which an internal RAS guarantee signal received from an internal RAS guarantee signal generating circuit is asserted, regardless of the control command instructing inactivation of the word line. In a normal operation mode, the internal RAS guarantee signal generating circuit activates the internal RAS guarantee signal until a prescribed period guaranteeing a restoring operation elapses, while in the test mode, it inactivates the internal RAS guarantee signal.

Abstract translation: 内部RAS生成电路基于从外部接收的控制命令，生成指示字线的激活的内部信号。 至少在从内部RAS保证信号发生电路接收到的内部RAS保证信号被断言的时段内，内部RAS产生电路激活内部信号，而不管指示字线失活的控制命令如何。 在正常工作模式下，内部RAS保证信号发生电路激活内部RAS保证信号，直到保证恢复运行的规定期间过去，而在测试模式下，内部RAS保证信号失效。

公开(公告)号：US20040164988A1

公开(公告)日：2004-08-26

申请号：US10669261

申请日：2003-09-25

Applicant: RENESAS TECHNOLOGY CORP. ,  RENESAS LSI DESIGN CORPORATION.

Inventor： Seiji Matsumoto

IPC: G06F013/00

CPC classification number: G09G5/003 ,  G09G2340/12

Abstract: An on-screen display unit includes OSD (on-screen display) RAMs each for storing data on one of OSD blocks to be subjected to OSD; a memory bus for transferring data to be stored to the OSD RAMs from a CPU; and an OSD local bus for transferring the data stored in the OSD RAMs to make the OSD. The OSD RAMs are supplied with the data to be stored through the control of switches alternately, and transfer the stored data to the OSD local bus 12 alternately. The on-screen display unit can cope with a high frequency OSD clock signal, and carry out the OSD normally.

Abstract translation: 屏幕显示单元包括OSD（屏幕显示）RAM，每个RAM用于存储要进行OSD的OSD块之一的数据; 用于从CPU传送要存储到OSD RAM的数据的存储器总线; 以及用于传送存储在OSD RAM中的数据以进行OSD的OSD本地总线。 交替地通过开关控制的OSD RAM来提供要存储的数据，并将存储的数据交替地传送到OSD本地总线12。 屏幕显示单元可以处理高频OSD时钟信号，并正常执行OSD。

公开(公告)号：US20040164428A1

公开(公告)日：2004-08-26

申请号：US10784276

申请日：2004-02-24

Applicant: Renesas Technology Corp. ,  Hitachi ULSI System Co., Ltd. ,  Hitachi Yonezawa Electronics Co., Ltd.

Inventor： Noriyuki Takahashi ,  Masayuki Suzuki ,  Kouji Tsuchiya ,  Takao Matsuura ,  Takanori Hashizume ,  Masahiro Ichitani ,  Kazunari Suzuki ,  Takafumi Nishita ,  Kenichi Imura ,  Takashi Miwa

IPC: H01L023/48

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.

Abstract translation: 将其上安装有多个半导体芯片的带状基板的背面真空吸附到模具的下半模，并且在该状态下，多个半导体芯片同时用树脂密封以形成密封构件。 此后，带状基板和密封构件从模具中释放并切割成多个半导体器件。 由此获得的半导体器件的安装可靠性得到改善。

公开(公告)号：US20040163246A1

公开(公告)日：2004-08-26

申请号：US10717718

申请日：2003-11-21

Applicant: Renesas Technology Corp. ,  MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

IPC: H05K003/10

CPC classification number: H01L21/76808 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400null C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

Abstract translation: 本发明的目的是提供一种具有掩埋多层布线结构的半导体器件，其中抗蚀剂图案的分辨率缺陷的产生被抑制，并且由分辨率缺陷引起的缺陷布线的产生减少。 在形成到达蚀刻停止膜（4）的通孔（7）之后，在通孔（7）打开的情况下，在300〜400℃进行退火。 作为退火方法，可以使用使用热板的方法和使用热处理炉的方法。 为了抑制对制造的下布线（20）的影响，通过使用热板进行约5〜10分钟的短时间的加热。 因此，残留在上部保护膜（6）和具有低介电常数的副产物残留在蚀刻阻挡膜（4）的界面上的层间电介质膜（5）的界面中的副产物和 排出具有低介电常数的层间绝缘膜（5），从而可以减少残留副产物的量。

公开(公告)号：US20040162936A1

公开(公告)日：2004-08-19

申请号：US10611865

申请日：2003-07-03

Applicant: Renesas Technology Corp.

Inventor： Akiko Hisasue ,  Junji Tateishi

IPC: G06F013/28

CPC classification number: G06Q10/00

Abstract: A material control system which provides for centralized control of a stock and an order so as to keep an appropriate control of materials in stock without differentiating a material which requires a regenerating process and a material which does not require a regenerating process. The material control system includes a master table storing information for controlling each of materials. The information is provided in an entry field of a regeneration control flag (104) indicating whether or not each of materials to be used in a manufacturing apparatus is regeneratable and an entry field of a regeneration order control flag (201) indicating whether or not a registered contractor is a seller or a regeneration contractor. The material control system further includes an order control section for making a purchase order for the materials and an order for a regenerating process, using the regeneration order control flag (201), and a stock control section for controlling a stock of the materials. The order control section and the stock control section are controlled in a centralized manner.

Abstract translation: 一种材料控制系统，其提供对库存和订单的集中控制，以便在不需要再生过程的材料和不需要再生过程的材料的情况下保持库存中材料的适当控制。 材料控制系统包括存储用于控制每个材料的信息的主表。 该信息被提供在再现控制标志（104）的输入字段中，指示制造装置中要使用的每种材料是否可再生，再生指令控制标志（201）的输入字段是否指示 注册承办商是卖方或再生承包商。 材料控制系统还包括使用再生顺序控制标志（201）和用于控制材料的库存的库存控制部分进行材料的采购订单和再生处理的订单的订单控制部分。 以集中方式控制订单控制部和库存控制部。