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公开(公告)号：US09688528B2
公开(公告)日：2017-06-27
申请号：US14970933
申请日：2015-12-16
Applicant: FUJIFILM Corporation
Inventor： Takahiro Sano , Takayuki Naono
IPC: H04R17/00 , B81B3/00 , G01C19/56 , G01P15/09 , H03H9/17 , H04R17/10 , H01L41/08 , H01L41/113 , H01L41/319 , H04R31/00 , B81C1/00 , H03H3/02 , H03H3/04 , G01P15/08
CPC classification number: B81B3/0072 , B81B2203/0127 , B81B2203/0353 , B81B2203/04 , B81C1/00666 , B81C2201/0112 , B81C2201/0169 , B81C2201/017 , B81C2201/0176 , G01C19/56 , G01P15/09 , G01P2015/084 , H01L41/0815 , H01L41/1138 , H01L41/319 , H03H9/17 , H03H2003/027 , H03H2003/0414 , H04R17/10 , H04R31/00 , H04R2201/003
Abstract: A producing method for a diaphragm-type resonant MEMS device includes forming a first silicon oxide film, forming a second silicon oxide film, forming a lower electrode, forming a piezoelectric film, forming an upper electrode, laminating the first silicon oxide film, the second silicon oxide film, the lower electrode, the piezoelectric film, and the upper electrode in this order on a first surface of a silicon substrate, and etching the opposite side surface of the first surface of the silicon substrate by deep reactive ion etching to form a diaphragm structure, in which the proportion R2 of the film thickness t2 of the second silicon oxide film with respect to the sum of the film thickness t1 of the first silicon oxide film and the film thickness t2 of the second silicon oxide film satisfies the following condition: 0.10 μm≦t1≦2.00 μm; and R2≧0.70.
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公开(公告)号：US20160264408A1
公开(公告)日：2016-09-15
申请号：US15031957
申请日：2014-10-15
Applicant: Swansea University
CPC classification number: B81C1/00111 , A61M37/0015 , A61M2037/003 , A61M2037/0053 , B81B2201/055 , B81C2201/0132 , B81C2201/0133 , B81C2201/0159 , B81C2201/0176 , B81C2201/0181 , C23C16/402
Abstract: A method of forming microneedles where through a series of coating and etching processes microneedles are formed from a surface as an array. The microneedles have a bevelled end and bore which are formed as part of the process with no need to use a post manufacturing process to finish the microneedle.
Abstract translation: 一种形成微针的方法，其中通过一系列涂层和蚀刻处理微针从表面形成为阵列。 微针具有倾斜的端部和孔，其形成为该过程的一部分，而不需要使用后制造工艺来完成微针。
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公开(公告)号：US09371223B2
公开(公告)日：2016-06-21
申请号：US14314703
申请日：2014-06-25
Inventor： Xuanjie Liu , Hongmei Xie , Liangliang Guo
CPC classification number: B81C1/00246 , B81B7/007 , B81B2207/015 , B81B2207/094 , B81C2201/0132 , B81C2201/0176 , B81C2203/0109 , B81C2203/036 , B81C2203/0735 , B81C2203/0771 , H01L41/0973
Abstract: MEMS devices and methods for forming the same are provided. A first metal interconnect structure is formed on a first semiconductor substrate to connect to a CMOS control circuit in the first semiconductor substrate. A bonding layer having a cavity is formed on the first metal interconnect structure, and then bonded with a second semiconductor substrate. A conductive plug passes through a first region of the second semiconductor substrate, through the bonding layer, and on the first metal interconnect structure. A second metal interconnect structure includes a first end formed on the first region of the second semiconductor substrate, and a second end connected to the conductive plug. Through-holes are disposed through a second region of the second semiconductor substrate and through a top portion of the bonded layer that is on the cavity to leave a movable electrode to form the MEMS device.
Abstract translation: 提供了MEMS器件及其形成方法。 第一金属互连结构形成在第一半导体衬底上以连接到第一半导体衬底中的CMOS控制电路。 在第一金属互连结构上形成具有空腔的接合层，然后与第二半导体衬底接合。 导电插塞穿过第二半导体衬底的第一区域，穿过接合层和第一金属互连结构。 第二金属互连结构包括形成在第二半导体衬底的第一区域上的第一端和连接到导电插塞的第二端。 通孔设置成穿过第二半导体衬底的第二区域并且通过位于空腔上的接合层的顶部以留下可移动电极以形成MEMS器件。
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公开(公告)号：US20150001632A1
公开(公告)日：2015-01-01
申请号：US14314703
申请日：2014-06-25
Inventor： XUANJIE LIU , HONGMEI XIE , LIANGLIANG GUO
CPC classification number: B81C1/00246 , B81B7/007 , B81B2207/015 , B81B2207/094 , B81C2201/0132 , B81C2201/0176 , B81C2203/0109 , B81C2203/036 , B81C2203/0735 , B81C2203/0771 , H01L41/0973
Abstract: MEMS devices and methods for forming the same are provided. A first metal interconnect structure is formed on a first semiconductor substrate to connect to a CMOS control circuit in the first semiconductor substrate. A bonding layer having a cavity is formed on the first metal interconnect structure, and then bonded with a second semiconductor substrate. A conductive plug passes through a first region of the second semiconductor substrate, through the bonding layer, and on the first metal interconnect structure. A second metal interconnect structure includes a first end formed on the first region of the second semiconductor substrate, and a second end connected to the conductive plug. Through-holes are disposed through a second region of the second semiconductor substrate and through a top portion of the bonded layer that is on the cavity to leave a movable electrode to form the MEMS device.
Abstract translation: 提供了MEMS器件及其形成方法。 第一金属互连结构形成在第一半导体衬底上以连接到第一半导体衬底中的CMOS控制电路。 在第一金属互连结构上形成具有空腔的接合层，然后与第二半导体衬底接合。 导电插塞穿过第二半导体衬底的第一区域，穿过接合层和第一金属互连结构。 第二金属互连结构包括形成在第二半导体衬底的第一区域上的第一端和连接到导电插塞的第二端。 通孔设置成穿过第二半导体衬底的第二区域，并通过位于空腔上的接合层的顶部部分留下可动电极以形成MEMS器件。
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165.发明授权Microelectromechanical device including an encapsulation layer of which a portion is removed to expose a substantially planar surface having a portion that is disposed outside and above a chamber and including a field region on which integrated circuits are formed, and methods for fabricating same 有权微电子机械装置包括一个封装层，一个部分被去除以暴露一个基本平坦的表面，该表面具有一个设置在室外的部分，并且包括形成有集成电路的场区域，以及用于制造集成电路的方法公开(公告)号：US08421167B2
公开(公告)日：2013-04-16
申请号：US12952895
申请日：2010-11-23
Applicant: Aaron Partridge , Markus Lutz , Silvia Kronmueller
Inventor： Aaron Partridge , Markus Lutz , Silvia Kronmueller
IPC: H01L21/00
CPC classification number: B81C1/00261 , B81B2207/015 , B81C1/00333 , B81C2201/0176 , B81C2203/0136 , H01L2924/0002 , H01L2924/00
Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.
Abstract translation: 这里描述和说明了许多发明。 在一个方面，本发明涉及MEMS器件，以及制造或制造MEMS器件的技术，其具有在最终封装之前封装在腔室中的机械结构。 当沉积时，封装机械结构的材料包括以下属性中的一个或多个：低拉伸应力，良好的阶梯覆盖，在经受后续加工时保持其完整性，不会显着和/或不利地影响 室中的机械结构（如果在沉积期间涂覆材料）和/或促进与高性能集成电路的集成。 在一个实施例中，封装机械结构的材料是例如硅（多晶，无定形或多孔，无论掺杂或未掺杂），碳化硅，硅 - 锗，锗或砷化镓。
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Patent Agency Ranking
166.发明申请公开(公告)号：US20080237756A1
公开(公告)日：2008-10-02
申请号：US11901826
申请日：2007-09-18
Applicant: Aaron Partridge , Markus Lutz , Silvia Kronmueller
Inventor： Aaron Partridge , Markus Lutz , Silvia Kronmueller
CPC classification number: B81C1/00261 , B81B2207/015 , B81C1/00333 , B81C2201/0176 , B81C2203/0136 , H01L2924/0002 , H01L2924/00
Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.
Abstract translation: 这里描述和说明了许多发明。 在一个方面，本发明涉及MEMS器件，以及制造或制造MEMS器件的技术，其具有在最终封装之前封装在腔室中的机械结构。 当沉积时，封装机械结构的材料包括以下属性中的一个或多个：低拉伸应力，良好的阶梯覆盖，在经受后续加工时保持其完整性，不会显着和/或不利地影响 室中的机械结构（如果在沉积期间涂覆材料）和/或促进与高性能集成电路的集成。 在一个实施例中，封装机械结构的材料是例如硅（多晶，无定形或多孔，无论掺杂或未掺杂），碳化硅，硅 - 锗，锗或砷化镓。
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公开(公告)号：US20080003784A1
公开(公告)日：2008-01-03
申请号：US11427272
申请日：2006-06-28
Applicant: Shaoher X. Pan
Inventor： Shaoher X. Pan
IPC: H01L21/20
CPC classification number: B81C1/00246 , B81B2201/047 , B81C2201/0176 , B81C2203/0721 , H01L21/02381 , H01L21/02532 , H01L21/0262
Abstract: A method of fabricating a micro structure includes depositing amorphous silicon over a substrate having an electric circuit at a temperature below 550° C. to form a first structure portion, wherein at least part of the first structure portion is configured to receive an electrical signal from the electric circuit.
Abstract translation: 制造微结构的方法包括在低于550℃的温度下在具有电路的衬底上沉积非晶硅，以形成第一结构部分，其中第一结构部分的至少一部分被配置为从 电路。
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168.发明授权Materials and methods for forming hybrid organic-inorganic anti-stiction materials for micro-electromechanical systems 有权用于形成微机电系统的混合有机 - 无机抗静电材料的材料和方法公开(公告)号：US07256467B2
公开(公告)日：2007-08-14
申请号：US10453933
申请日：2003-06-04
Applicant: Jason S. Reid , Nungavram S. Viswanathan
Inventor： Jason S. Reid , Nungavram S. Viswanathan
CPC classification number: C09D4/00 , B81B3/0005 , B81C1/0096 , B81C2201/0176 , B81C2201/112 , B82Y30/00 , C08G77/00 , C08G77/04 , C08G77/24
Abstract: A micro-electromechanical device is formed on a substrate. The device has sliding, abrading or impacting surfaces. At least one of these surfaces is covered with an anti-stiction material. The anti-stiction material is provided from a slicon compound precursor (e.g. silane, silanol) or multiple silicon compound precursors. Preferably the precursor(s) is fluorinated—more preferably perfluorinated, and is deposited with a solvent as a low molecular weight oligomer or in monomeric form. Examples include silanes (fluorinated or not) with aromatic or polycyclic ring sturctures, and/or silanes (fluorinated or not) having alkenyl, alkynyl, epoxy or acrylate groups. Mixtures either or both of these groups with alkyl chain silanes (preferably fluorinated) are also contemplated.
Abstract translation: 在基板上形成微机电装置。 该装置具有滑动，研磨或冲击表面。 这些表面中的至少一个被抗静电材料覆盖。 抗粘性材料由Slico化合物前体（例如硅烷，硅烷醇）或多种硅化合物前体提供。 优选地，前体被氟化 - 更优选全氟化，并且以溶剂作为低分子量低聚物或以单体形式沉积。 实例包括具有芳族或多环结构的硅烷（氟化或非氟化），和/或具有烯基，炔基，环氧基或丙烯酸酯基团的硅烷（氟化或非氟化）。 这些基团中的一个或两个与烷基链硅烷（优选氟化）混合也是可以预料的。
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169.发明申请公开(公告)号：US20060108652A1
公开(公告)日：2006-05-25
申请号：US11323920
申请日：2005-12-30
Applicant: Aaron Partridge , Markus Lutz , Silvia Kronmueller
Inventor： Aaron Partridge , Markus Lutz , Silvia Kronmueller
CPC classification number: B81C1/00261 , B81B2207/015 , B81C1/00333 , B81C2201/0176 , B81C2203/0136 , H01L2924/0002 , H01L2924/00
Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.
Abstract translation: 这里描述和说明了许多发明。 在一个方面，本发明涉及MEMS器件，以及制造或制造MEMS器件的技术，其具有在最终封装之前封装在腔室中的机械结构。 当沉积时，封装机械结构的材料包括以下属性中的一个或多个：低拉伸应力，良好的阶梯覆盖，在经受后续加工时保持其完整性，不会显着和/或不利地影响 室中的机械结构（如果在沉积期间涂覆材料）和/或促进与高性能集成电路的集成。 在一个实施例中，封装机械结构的材料是例如硅（多晶，无定形或多孔，无论掺杂或未掺杂），碳化硅，硅 - 锗，锗或砷化镓。
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170.发明申请Microelectromechanical systems having trench isolated contacts, and methods for fabricating same 有权具有沟槽隔离触点的微机电系统及其制造方法公开(公告)号：US20040245586A1
公开(公告)日：2004-12-09
申请号：US10455555
申请日：2003-06-04
Inventor： Aaron Partridge , Markus Lutz , Silvia Kronmueller
IPC: H01L021/00 , H01L027/14 , H01L029/82 , H01L021/44
CPC classification number: B81C1/00301 , B81B2207/015 , B81B2207/095 , B81C2201/0176 , B81C2203/0136
Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging and a contact area disposed at least partially outside the chamber. The contact area is electrically isolated from nearby electrically conducting regions by way of dielectric isolation trench that is disposed around the contact area. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.
Abstract translation: 这里描述和说明了许多发明。 一方面，本发明涉及MEMS器件，以及制造或制造MEMS器件的技术，其具有在最终封装之前封装在腔室中的机械结构以及至少部分地设置在腔室外部的接触区域。 接触区域通过设置在接触区域周围的绝缘隔离沟槽与附近的导电区域电隔离。 当沉积时，封装机械结构的材料包括以下属性中的一个或多个：低拉伸应力，良好的阶梯覆盖，在经受后续加工时保持其完整性，不会显着和/或不利地影响 室中的机械结构（如果在沉积期间涂覆材料）和/或促进与高性能集成电路的集成。 在一个实施例中，封装机械结构的材料是例如硅（多晶，无定形或多孔，无论掺杂或未掺杂），碳化硅，硅 - 锗，锗或砷化镓。
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