中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

929 records (took 0.042 seconds)

    Representing a cache line bit pattern via meta signaling
    175.
    发明授权
    Representing a cache line bit pattern via meta signaling 有权
    通过元信号表示高速缓存行位模式

    公开(公告)号：US09563251B2

    公开(公告)日：2017-02-07

    申请号：US14142813

    申请日：2013-12-28

    Applicant: Intel Corporation

    Inventor： Saher Abu Rahme ,  Christopher E. Cox ,  Joydeep Ray

    IPC: G06F12/08 ,  G06F1/32

    CPC classification number: G06F12/0804 ,  G06F1/3225 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0897 ,  G06F2212/60

    Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

    Abstract translation: 具有模式识别机制的高速缓存控制器可以识别高速缓存行中的模式。 代替将高速缓存行的整个数据传送到目的地设备，高速缓存控制器可以生成元信号以表示所识别的位模式。 高速缓存控制器将元信号发送到目的地代替高速缓存行的至少一部分。

    Isochronous agent data pinning in a multi-level memory system
    176.
    发明授权
    Isochronous agent data pinning in a multi-level memory system 有权
    多级存储器系统中的同步代理数据固定

    公开(公告)号：US09542336B2

    公开(公告)日：2017-01-10

    申请号：US14133097

    申请日：2013-12-18

    Applicant: INTEL CORPORATION

    Inventor： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

    IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12

    CPC classification number: G06F12/126

    Abstract: A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

    Abstract translation: 处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。 钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。 钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。 此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中 并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。

    Frequency selection granularity for integrated circuits
    177.
    发明授权
    Frequency selection granularity for integrated circuits 有权
    集成电路的频率选择粒度

    公开(公告)号：US09343126B2

    公开(公告)日：2016-05-17

    申请号：US13730607

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Harikrishna B. Baliga ,  Peter J. Smith ,  Joydeep Ray

    IPC: G06F1/04 ,  G11C8/18 ,  H03L7/18 ,  H03L7/07

    CPC classification number: G11C8/18 ,  H03L7/07 ,  H03L7/18

    Abstract: Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.

    Abstract translation: 时钟信号发生电路。 耦合倍频器以接收时钟信号并产生倍频时钟信号。 开关电路被耦合以接收至少两个参考时钟信号。 开关电路响应于参考选择信号提供参考时钟信号之一。 耦合锁相环（PLL）以接收倍频时钟信号和所选择的参考时钟信号。 PLL产生输出时钟信号。

    PROGRESSIVE MULTISAMPLE ANTI-ALIASING
    180.
    发明申请
    PROGRESSIVE MULTISAMPLE ANTI-ALIASING 有权

    公开(公告)号：US20250104326A1

    公开(公告)日：2025-03-27

    申请号：US18882285

    申请日：2024-09-11

    Applicant: Intel Corporation

    Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Michael J. Norris

    IPC: G06T15/00 ,  G06T11/40

    Abstract: One embodiment provides a graphics processor comprising an interface to a system interconnect and a graphics processor coupled to the interface, the graphics processor comprising circuitry configured to compact sample data for multiple sample locations of a pixel, map the multiple sample locations to memory locations that store compacted sample data, the memory locations in a memory of the graphics processor, apply lossless compression to the compacted sample data, and update a compression control surface associated with the memory locations, the compression control surface to specify a compression status for the memory locations

Patent Agency Ranking