公开(公告)号：JP2001156640A

公开(公告)日：2001-06-08

申请号：JP34148299

申请日：1999-11-30

Applicant: YAMAHA CORP

Inventor： TODA AKIHIKO ,  MAEJIMA TOSHIO ,  NORO MASAO

IPC: H03M1/68 ,  H03M1/74 ,  H03M1/76

Abstract: PROBLEM TO BE SOLVED: To provide a resistor string digital/analog converter that can increase the bits of converted data without increasing number of resistors. SOLUTION: High-order four bits of data to be converter are applied to a decoder 1 and low-order four bits are applied to a decoder 3 via an inversion circuit 2. The decoder 1 decodes the high-order four bits and makes one of FET F0-F15 conductive based on the decoding result. Thus, one of voltages at connecting points of resistors r0-r15 connected in series is selected and applied to an operational amplifier 6. Similarly a voltage corresponding to the low-order four bits of the data to be converted is applied to an operational amplifier 7. Then an output of the operational amplifier 7 is divided into 1/16 by resistors ra, rb, this voltage is added to a voltage applied to the operational amplifier 6 to obtain an analog voltage after conversion.

公开(公告)号：JP2001026133A

公开(公告)日：2001-01-30

申请号：JP19958399

申请日：1999-07-13

Applicant: YAMAHA CORP

Inventor： SOGO AKIRA ,  NORO MASAO ,  MUROI KUNIMASA ,  TODA KOJI

IPC: B41J2/385 ,  B41C1/10

Abstract: PROBLEM TO BE SOLVED: To print at high speed in high quality in an electric solidification type printing. SOLUTION: This printing method comprises a line timing signal generating process S3 wherein a start of each line of gradation data is indicated before or after the generation of the gradation data and a parallel conversion process S4 wherein the gradation data generated in a gradation data generating process S2 is converted to parallel data corresponding to the number of electrodes. The printing method further comprises a gradation value holding process S5 wherein each of the gradation values obtained by the conversion in the parallel conversion process S4, a parallel driving control process S6 wherein the gradation values are outputted at roughly the same time after one line of gradation values are held in the gradation value holding process S5 and an electrode driving process S7 wherein ink on a printing drum at a position opposite to the electrode is solidified by driving the electrode based on the gradation values.

公开(公告)号：JPH11260093A

公开(公告)日：1999-09-24

申请号：JP5972798

申请日：1998-03-11

Applicant: YAMAHA CORP

Inventor： TODA AKIHIKO ,  NORO MASAO ,  MAEJIMA TOSHIO

IPC: G11C27/02 ,  H03H11/26 ,  H03H19/00

Abstract: PROBLEM TO BE SOLVED: To provide a delay circuit in which low frequency noise disturbance can be removed. SOLUTION: At the time of writing, an input analog signal Vin is stored in odd number memory cell M1, M3,..., Mn-1 and an inverted input analog signal Vin is stored in even number memory cell M2, M4,..., Mn. At the time of reading, a signal read out from even number memory cell M2, M4,..., Mn is inverted and combined, by a switch SH0, with a signal read out from odd number memory cell M1, M3, ..., Mn-1 to produce an output analog signal Vout. When a low frequency noise is mixed in the delay circuit, a voltage value stored in a capacitor C1-Cn is varied but since it is read out while repeating forward and reverse rotation, noise component can be shifted to a separable high region frequency.

公开(公告)号：JPH11146499A

公开(公告)日：1999-05-28

申请号：JP30218397

申请日：1997-11-04

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA ,  NORO MASAO

IPC: H04S5/00

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive pseudo stereo circuit in simple configuration. SOLUTION: A phase shift circuit 1 is a means for shifting the phase of an input monophonic signal Min just for an amount corresponding to its frequency, and its gain is higher than a fixed level over all the frequency bands of the input monophonic signal Min and becomes a peak near a frequency where the phase shift amount is -π. A multiplier 2 and an adder 4 mix a signal inverting the phase of an output signal from the phase shift circuit 1 and the input monophonic signal Min in a prescribed mixing ratio and output the result as the audio signal of an L channel. A multiplier 3 and an adder 5 mix the output signal of the phase shift circuit 1 and the input monophonic signal Min in a prescribed mixing ratio and output the result as the audio signal of an R channel.

公开(公告)号：JPH11122112A

公开(公告)日：1999-04-30

申请号：JP28085097

申请日：1997-10-14

Applicant: YAMAHA CORP

Inventor： HIRANO MASAZO ,  NORO MASAO

IPC: H03M1/08 ,  H03M3/02

Abstract: PROBLEM TO BE SOLVED: To attain high accuracy for an analog characteristic of D/A conversion with a simple configuration. SOLUTION: When detection data Db are fed to a waveform shaping section 31, a shaped detection data signal Db' is generated, based on a clock CK and the detection data Db. The shaped detection data signal Db' is given to a low pass filter 32, where a high frequency component is eliminated and the result is compared with a reference voltage Vr at a comparator circuit 33, which produces an error signal GS. Then an output buffer 34 converts impedance and the error signal GS is fed to the waveform shaping section 31 and the section 4. The waveform shaping section 4 adjusts level of pulses of 1-bit data Da so as to areas of the pulses are equal to each other to generate corrected 1-bit data Da'.

公开(公告)号：JPH10178456A

公开(公告)日：1998-06-30

申请号：JP33606496

申请日：1996-12-16

Applicant: YAMAHA CORP

Inventor： TODA AKIHIKO ,  NORO MASAO

IPC: H03K5/003 ,  H03K5/08 ,  H04L25/03 ,  H04L25/06 ,  H04L25/49

Abstract: PROBLEM TO BE SOLVED: To provide an information identification circuit that improves the noise margin. SOLUTION: Upon the receipt of an input signal Vin with Vin(-)>Va, a gate voltage Vb of a FETm7 is increased and the FETm7 becomes conductive. In this case, since the FETm7 receives a current via a resistor 51, the voltage Va is decreased resulting that an output voltage Vc of an operational amplifier 60 is increased. In this case, the output voltage Vc acts like a bias voltage on the Vin(+) and Vin(-), then the Vin(+) and Vin(-) are increased as the voltage Vc rises. On the other hand, since a threshold voltage Vr of comparators 70, 71 is fixed, the relation between the bias voltage Vc and the threshold voltage Vr is relatively adjusted with respect to the input level. Thus, the noise margin is optimized.

公开(公告)号：JPH10155199A

公开(公告)日：1998-06-09

申请号：JP21219197

申请日：1997-08-06

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA ,  NORO MASAO

IPC: H04R3/04 ,  H03G5/02 ,  H03G5/12 ,  H04S1/00 ,  H04S7/00

Abstract: PROBLEM TO BE SOLVED: To provide a sound field extending device in which LSI processing is easily attained by integrating a bass control function in an amplitude phase conversion circuit so as to eliminate the need for a capacitor of a large capacitance. SOLUTION: An amplitude phase conversion circuit 1a(1b) has an inverting amplifier 2a(2b), an amplitude phase characteristic providing circuit 3a(3b) providing a prescribed amplitude and phase characteristic to the output, and a feedback means that adds the output of the amplitude phase characteristic providing circuit 3a(3b) and the output of the inverting amplifier 2a(2b) to each input signal and feeds back the result to the inverting amplifier 2a(2b). The output of the inverting amplifier 2a and the output of the amplitude phase characteristic providing circuit 3b are added by an adder means 6a and the output of the inverting amplifier 2b and the output of the amplitude phase characteristic providing circuit 3a are added by an adder means 6a. D/A converters 5a, 5b are provided to feedback paths of the outputs of the amplitude phase characteristic providing circuits 3a(3b) to adjust the feedback signal level for bass control.

公开(公告)号：JPH08307273A

公开(公告)日：1996-11-22

申请号：JP13483395

申请日：1995-05-08

Applicant: YAMAHA CORP

Inventor： NORO MASAO

IPC: H03M1/68 ,  H03M1/70 ,  H03M1/74

Abstract: PURPOSE: To provide the D/A converter circuit in which number of bits is simply extended without enlarging in scale. CONSTITUTION: The D/A converter circuit is provided with a D/A converter 1 receiving high-order 14-bit data among 16-bit digital data and a current mirror circuit 3 generating constant currents I2, I3 corresponding to digital data of low-order 2-bit. An output of the current mirror circuit 3 is switched by a current changeover circuit 4 and the selected output is added to an output of the D/A converter 1 by a voltage follower circuit 2. The currents I2, I3 corresponding to the low-order 2-bit are set to be I2=2×I3 depending on the size of transistors(TRs) Q2, Q3.

公开(公告)号：JPH08307265A

公开(公告)日：1996-11-22

申请号：JP13483195

申请日：1995-05-08

Applicant: YAMAHA CORP

Inventor： NORO MASAO

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/08 ,  H03M1/66

Abstract: PURPOSE: To provide the D/A converter circuit in which the linearity improvement effect equivalent to that by juxtaposition of lots of D/A converters is made to obtain, regardless of a few D/A converters. CONSTITUTION: A random signal voltage A obtained by a random signal generating circuit 2 is added/subtracted to/from a digital signal to be given to two multi-bit D/A converters 1a, 1b by adders 3a, 3b as an offset voltage A, -A whose sum is zero. D/A conversion is conducted along with a nonlinear curve whose reference point is shifted by the offset voltages changing at random timewise and analog outputs from the D/A converters 1a, 1b are added by an adder 4 and the sum is extracted. Then, the same equivalent effect as averaging outputs of lots of D/A converters on time base is obtained.

公开(公告)号：JPH08307164A

公开(公告)日：1996-11-22

申请号：JP13284195

申请日：1995-05-02

Applicant: YAMAHA CORP

Inventor： NORO MASAO

IPC: H03F3/45 ,  H03F3/30 ,  H03F3/34

Abstract: PURPOSE: To obtain the push-pull output operational amplifier with a new configuration. CONSTITUTION: An input signal is give respectively to transistors (TRs) Q1, Q2 of a first stage differential amplifier 38 from input terminals 58, 60. Drain outputs of the TRs Q1, Q2 are respectively given to TRs Q5, Q6 of a next stage differential amplifier 40. An output of the TR Q5 is given to an output by a current mirror circuit comprising TRs Q7, Q12. An output of the TR Q6 is given to a current mirror circuit comprising TRs Q8, Q9 at first and then given to an output by a current mirror circuit comprising TRs Q10, Q11. Through the connection above, a differential output of the TRs Q5, Q6 is converted into a push-pull output of TRs Q11, Q12 and led to an output terminal 56.